Senior Digital ASIC Design Engineer

Bonatti; Parma; Ibrido; EUR 50.000 - 70.000; Tempo pieno

Descrizione del lavoro

A semiconductor design firm is looking for a Senior Digital ASIC Design Engineer to join their expanding team. In this role, you will work on low-power high-definition video compression and AI technologies alongside multi-skilled engineers. The ideal candidate will possess a solid background in Digital ASIC Design and strong skills in Verilog/SystemVerilog. Flexible working is offered, allowing you to explore the latest technologies in an innovative environment.

Competenze

• Solid background in Digital ASIC Design and IP integration.
• Strong Verilog / SystemVerilog skills; UVM verification knowledge is a plus.
• Hands-on with RTL design, simulation, and technical documentation.

Mansioni

• Work in a growing team of multi-skilled engineers across various disciplines.
• Contribute to low-power, high-definition video compression and AI applications.

Conoscenze

Digital ASIC Design

Verilog / SystemVerilog

RTL design

Image/video processing

FPGA implementation

Formazione

Degree in Computer Science, Computer Engineering, Electrical Engineering, or similar

Descrizione del lavoro

Principal Recruitment Consultant at IC Resources - Semiconductor Engineering division

This client is looking for a Senior Digital ASIC Design Engineer to join their team.

Working for a US-based, fabless semiconductor design company, focusing on low-power, high-definition and Ultra HD video compression, image processing, and computer vision processors for AI applications.

You will be working in a growing team of multi-skilled engineers across technical disciplines such as digital/analog / mixed-signal in design, verification and physical design.

Offering flexible working and an opportunity to work on the latest technologies and methods!

Qualifications

• Degree in Computer Science, Computer Engineering, Electrical Engineering, or similar
• Solid background in Digital ASIC Design and IP integration
• Strong Verilog / SystemVerilog skills; UVM verification knowledge is a plus
• Hands‑on with RTL design, simulation, and technical documentation
• Familiar with ASIC synthesis; FPGA implementation experience is a bonus
• Understanding of the full digital design flow (RTL, verification, synthesis, gate‑level simulation)
• Exposure to image/video processing, computer vision, or machine learning is advantageous

Contact

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/

Seniority level

• Mid-Senior level

Employment type

• Full-time

Industry

• Staffing and Recruiting