Design Architect Front-End M/F

STMicroelectronics; Genova; In loco; EUR 30.000 - 40.000; Tempo pieno

Descrizione del lavoro

A leading semiconductor company in Italy is seeking a junior IP engineer to join their IP management team. This role involves supporting the adoption of various IPs and collaborating throughout the SoC/ASIC design process. Candidates should have a Master’s degree and a strong willingness to learn. The internship offers flexible work arrangements and development opportunities within a multicultural environment.

Servizi

Flexible work arrangements

Company canteen

Shuttle service

Free parking

Competenze

• Good university knowledge of SoC design flow, semiconductor processes, firmware, and software.
• Business fluent in English.

Mansioni

• Support adoption of various IPs throughout the SoC/ASIC design process.
• Collaborate with the IP management team.
• Deliver solutions and problem-solving.

Conoscenze

Teamwork

Problem-solving

Understanding SoC design flow

Multicultural attitude

Formazione

Master’s degree

Descrizione del lavoro

Job description

STMicroelectronics (STM) supports leading-edge system companies in optical, wired, and wireless infrastructures by providing complete design platforms and production capabilities for high-end SoC (System On Chip) / ASIC (Application Specific Integrated Circuit) in advanced FinFET Technologies (7, 5, and 3 nm nodes).

For these SoC/ASICs, the availability of pre-defined functional blocks, silicon-validated and compliant with specific market standards—named “Intellectual Properties” (IP)—is crucial. These IPs leverage the latest FinFET technology nodes' extreme integration capabilities, allowing STM customers to enhance their SoC with new functionalities, enabling entry into new markets or products without significantly affecting time to market or R&D costs.

In this complex context, STM’s wireless and optical infrastructure ASIC business is expanding its R&D organization and opening a new position for a junior IP engineer, who will be part of our IP management team. The IP engineer supports the adoption of various IPs, including CPUs, high-speed interfaces such as PCIe-USB / High-Speed SerDes, Ethernet, and Memory interfaces (DDR, LPDDR), throughout the SoC/ASIC design process—from early definition to silicon validation.

Profile

Who are we looking for:

• “Learn and deliver” attitude; understanding problems and providing solutions is key.
• Strong teamwork and multicultural attitude. No solo work; team matters.
• Willingness to be challenged. Our SoCs always utilize the latest technologies and solutions available in the market.
• Good university knowledge of SoC design flow, semiconductor processes, firmware, and software.

What we offer

• International, multicultural internship in a large high-tech multinational, a key player in the semiconductor industry.
• Opportunity to participate in transformational change programs.
• Strong development opportunities in strategic and operational HR initiatives to grow HR and project management skills.
• Coaching and guidance from senior resources, interaction with HR and business colleagues, leaders, and providers to develop leadership skills.
• Flexible work arrangements.
• Reimbursement of expenses.
• Company canteen, shuttle service, and free parking.
• Smart casual dress code.

The internship will be based at our Castelletto site.

The employment search is addressed to candidates of both genders, under Law 10.04.1991 n. 125, as amended by Legislative Decree n. 198/2006, which guarantees gender equality at work.

Position details

• Location: Europe, Italy, Castelletto
• Education level: Master’s degree (5)
• Experience: Less than 2 years
• Languages: English (business fluent)
• Desired start date: 01/01/2024