Hardware Verification Engineer

Baya Systems; Remote; GBP 70,000 - 90,000; Full time

Job summary

A technology company is seeking a Senior Hardware Verification Engineer to collaborate on creating test plans for complex interconnectivity IPs. The ideal candidate will have over 8 years of experience in SOC-level verification, proficiency in Verilog, SystemVerilog, and a strong understanding of UVM-based testbenches. This remote position in England offers the opportunity to shape technology solutions while working with dynamic teams. Candidates should possess excellent problem-solving skills and effective communication abilities.

Qualifications

• 8+ years and current hands-on experience in block-level / IP-level / SOC-level verification.
• Deep experience with UVM-based testbenches.
• Familiarity with ARM AMBA protocols such as AXI, APB, and AHB.

Responsibilities

• Collaborate with design and architecture teams to create test plans for configurable IPs.
• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards.
• Work with design and DV engineers to implement the test plan and debug failures.

Skills

Verilog

SystemVerilog

UVM-based testbenches

Python

Problem-solving skills

Communication skills

Attention to detail

Education

BS / MS in Electrical Engineering, Computer Engineering or Computer Science

Tools

EDA tools for simulation and debugging

Job description

Job Title:

Senior Hardware Verification Engineer

Location:

England, United Kingdom (Remote anywhere inside the country)

About the Role:

We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities:

• Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
• Write UVM / SystemVerilog code to implement the test plan, checkers and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Qualifications:

• BS / MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands-on experience in block-level / IP-level / SOC-level verification
• Proficiency in Verilog, SystemVerilog
• Familiarity with industry-standard EDA tools for simulation and debug
• Deep experience with UVM-based testbenches
• Experience with modern programming languages like Python
• Knowledge of ARM AMBA protocols such as AXI, APB, and AHB
• Understanding of ARM CHI protocol is a plus
• Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs
• Experience with formal verification techniques, emulation platforms is a plus
• Excellent problem-solving skills and attention to detail
• Strong communication and collaboration skills

[e-mail]