Senior Digital Design Engineer

Beagle; Madrid; Presencial; EUR 70.000 - 90.000; Jornada completa

Descripción de la vacante

A technology company in Madrid is seeking a PCIe Lead / Senior Digital Design Engineer to design and integrate PCIe solutions in complex SoC / ASIC environments. Candidates should have over 4 years of experience, strong skills in PCIe design, and proficiency in RTL design. This permanent role offers the opportunity to work with cross-functional teams in a dynamic setting.

Formación

• 4+ years industrial experience for Engineer, 6+ years for Lead.
• Strong hands-on experience with PCIe.
• Solid background in SoC / ASIC IP integration.

Responsabilidades

• Own the architecture and lead the RTL implementation of PCIe subsystems.
• Drive efficient interaction between PCIe block and CPU clusters using AMBA-CHI coherency.
• Integrate and verify IPs within large SoC environments.

Conocimientos

PCIe design and integration

RTL design (Verilog or VHDL)

SoC / ASIC IP integration

Basic block-level testing

Familiarity with AXI, CHI, or AHB

Educación

Bachelor's degree or higher

Descripción del empleo

ROLE

PCIe Lead / Senior Digital Design Engineer

LOCATION

Barcelona, Spain

SALARY

Negotiable

DURATION

Permanent

We’re looking for an experienced engineer to take a leading role in the design and integration of PCIe solutions within complex SoC / ASIC environments. If you’re passionate about microprocessor architecture, high-speed I / O, and building high-performance subsystems, this role puts you at the centre of it.

What you’ll be doing

• Own the architecture and lead the RTL implementation of PCIe subsystems


• Drive efficient interaction between the PCIe block and CPU clusters using AMBA-CHI coherency


• Integrate and verify IPs within large SoC environments


• Work closely with cross-functional teams of digital, verification, and architecture experts

What you’ll bring

• 4+ years industrial experience (Engineer) or 6+ years (Lead)


• Strong hands-on experience with PCIe (design and / or integration)


• Solid background in SoC / ASIC IP integration


• Proficiency in RTL design (Verilog or VHDL)


• Experience with basic block-level testing


• Familiarity with at least one protocol : AXI, CHI, or AHB

Nice to have

• Master’s degree or PhD


• Knowledge of C++, Python, Perl, Bash, or TCL


• Experience working with version control (git, svn)


• Understanding of coherency protocols


• Experience with CXL


• Exposure to common digital design tools (Synthesis, STA, CDC, Lint, etc.)