Senior ASIC Engineer / Technical Lead

Openchip And Software Technologies SL; Barcelona; Híbrido; EUR 100.000 - 140.000; Jornada completa

Descripción de la vacante

A microelectronics firm in Barcelona is seeking a Senior ASIC Engineer / Technical Lead to oversee ASIC and SoC developments, particularly with RISC-V systems. The ideal candidate will have over 15 years of experience and expertise in digital design languages. The role offers a hybrid working environment, competitive compensation, and opportunities for collaboration with leading research institutes. Candidates fluent in English are encouraged to apply.

Servicios

Flexible working conditions

Competitive remuneration

Collaboration with top-tier research institutions

Formación

• 15+ years of experience in ASIC and SoC development within microelectronics environments.
• Proven experience covering the complete ASIC flow: RTL, synthesis, place & route, verification, and sign-off.
• Deep understanding of EDA tools and ASIC / FPGA design methodologies.

Responsabilidades

• Lead and contribute to full ASIC development flows, from system and RTL design to GDSII sign-off.
• Design, implement, and maintain FPGA-based prototypes to validate architectures.
• Act as primary technical point of contact for hardware design and ASIC/SoC development.

Conocimientos

Digital design languages (VHDL, Verilog, SystemVerilog)

FPGA prototyping experience (Xilinx, Intel/Altera)

RISC-V architecture knowledge

Communication skills

Educación

Master’s degree in Electronics Engineering or a related field

Herramientas

EDA tools

Descripción del empleo

The Role

In the Innovation department we are seeking a highly experienced Senior ASIC Engineer / Technical Lead to drive the architecture, design, and implementation of advanced ASIC and SoC developments, with a strong focus on RISC-V-based systems, high-performance digital design, and complex mixed research–industry environments.

You will play a key role in leading end-to-end ASIC developments, from architectural definition and RTL design through synthesis, physical implementation, silicon validation, and FPGA-based prototyping. The role combines hands‑on technical leadership with acting as a technical interface with public research centers and universities, ensuring smooth collaboration and high-quality outcomes in externally contracted hardware developments.

Key Responsibilities

• Lead and contribute to full ASIC development flows, from system and RTL design to GDSII sign-off.
• Define and validate digital architectures, including RISC-V SoCs and domain‑specific accelerators.
• Drive technical decisions related to RTL design, verification strategies, synthesis, P&R, and sign-off.
• Design, implement, and maintain FPGA‑based prototypes to validate architectures, subsystems, and system‑level functionality ahead of tape‑out.
• Use FPGA prototyping as a vehicle for early software bring‑up, performance evaluation, and risk reduction.
• Interface with foundries, EDA vendors, and external industrial partners during design, fabrication, and validation phases.
• Act as primary technical point of contact for hardware design and ASIC / SoC development contracts with public research centers and universities.
• Coordinate, supervise, and technically validate externally contracted hardware design activities, ensuring alignment with internal architectures, schedules, and quality requirements.
• Facilitate effective collaboration and technology transfer between internal engineering teams and public research institutions.
• Provide technical leadership and mentoring to junior engineers and project teams.
• Contribute to European collaborative R&D projects, representing the company in technical discussions with research institutes, universities, and industrial partners.
• Support technology scouting and evaluation of new process nodes, tools, and design methodologies.

Required Qualifications

• Master’s degree in Electronics Engineering or a related field.
• 15+ years of experience in ASIC and SoC development within microelectronics environments.
• Proven experience covering the complete ASIC flow: RTL, synthesis, place & route, verification, and sign-off.
• Strong expertise in digital design languages (VHDL, Verilog, SystemVerilog).
• Hands‑on experience with FPGA prototyping, including architecture validation and system-level bring‑up (Xilinx, Intel / Altera or equivalent).
• Solid background in RISC-V architectures and complex SoC integration.
• Deep understanding of EDA tools and ASIC / FPGA design methodologies.
• Demonstrated ability to work effectively in collaborative R&D environments involving external stakeholders such as research institutes and universities.
• Excellent communication skills and ability to act as a technical interface between industrial and academic teams.
• Fluent in English; Spanish and / or Catalan are a plus.

Desirable Qualifications

• Prior professional experience in public research centers or universities (e.g. CSIC, national laboratories, or equivalent European research institutions).
• Experience in medical electronics, imaging systems, or advanced detector readout electronics.
• Previous involvement in EU‑funded collaborative R&D projects (Horizon Europe, Chips JU, IPCEI, etc.).
• Experience across multiple technology nodes (e.g. GF22, TSMC65 / 130, XFAB180, AMS).

What Do We Offer?

• Join a highly innovative microelectronics company working at the forefront of RISC‑V and advanced SoC technologies.
• Opportunity to play a key technical leadership role bridging industry and public research.
• Collaboration with top‑tier research institutions and industrial partners across Europe.
• Flexible working conditions and hybrid work environment.
• Competitive remuneration aligned with seniority and expertise.
• Position based in Barcelona.

We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.

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