Sr. Staff Engineer, SoC RTL Design - Fabric

Tenstorrent Inc.; Toronto; Hybrid; CAD 137,000 - 689,000; Full time

Job summary

A leading AI technology company is seeking a Sr. Staff SoC RTL Design Engineer specializing in Fabric for their Toronto office. This hybrid role involves leading the architecture, implementation, and optimization of high-performance on-chip interconnects for next-gen AI workloads. Ideal candidates will have deep expertise in NoC microarchitectures and RTL design. A competitive compensation package ranging from $100k - $500k is offered, depending on experience and skills.

Benefits

Highly competitive compensation package

Benefits

Qualifications

• Senior digital design leader with NoC and fabric microarchitectures experience.
• Proficient in ASIC flows and RTL development.
• Experience with performance tuning and scalable SoC integration.

Responsibilities

• Lead architecture and implementation of custom fabric IP.
• Drive performance-aware design for compute-heavy interconnects.
• Contribute to validation flows using emulation and FPGA prototyping.

Skills

On-chip fabric expertise

RTL development (SystemVerilog/Verilog)

PPA optimization

Collaboration and technical leadership

Protocol compliance (e.g., AXI, CHI)

Job description

Tenstorrent is leading the industry on cutting‑edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high‑performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a Sr. Staff SoC RTL Design Engineer specializing in Fabric to lead the architecture, implementation, and optimization of high‑performance on‑chip interconnects and fabrics for next‑gen AI and compute workloads. This role is ideal for senior engineers with deep expertise in NoC and fabric microarchitectures who thrive at the intersection of RTL design, performance tuning, and scalable SoC integration.

This role is hybrid, based out of Toronto, Boston, Ottawa or Santa Clara.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A senior digital design leader with deep expertise in on‑chip fabric and NoC microarchitectures for high‑performance SoCs.
• Proficient in RTL development (SystemVerilog/Verilog) for complex interconnects, with hands‑on experience across full ASIC flows.
• Expert in PPA optimization for low‑latency, high‑bandwidth fabrics supporting AI workloads and multi‑die integration.
• A collaborative technical driver skilled in spec definition, peer reviews, and cross‑functional team planning.
• Experienced in prior on‑chip fabric and NoC designs, including protocol compliance (e.g., AXI, CHI) and coherency mechanisms.

What We Need

• Lead architecture and RTL implementation of custom fabric IP, NoC routers, switches, and SoC interconnect components.
• Drive performance‑aware design decisions for compute‑heavy interconnects, ensuring scalability and efficiency.
• Contribute to validation flows using emulation, FPGA prototyping, or UVM to verify fabric functionality.
• Support synthesis, timing closure, power optimization, and clean handoffs to backend teams.
• Mentor junior engineers on fabric best practices, automation, and integration with CPU/memory subsystems.

What You Will Learn

• How cutting‑edge AI chips are built, from fabric spec to silicon tapeout.
• What it takes to collaborate with teams on novel processor, accelerator, and memory architectures.
• How to blend custom fabric logic with standard SoC elements for optimal power and scale.
• How cross‑functional workflows integrate across design, DV, physical, and firmware teams.
• Advanced techniques in on‑chip fabric and NoC design for next‑generation scalable AI platforms.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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