Senior Design Verification Engineer – AI and Video Processor IP

Qualcomm; Markham; On-site; CAD 104,000 - 155,000; Full time

Job summary

A global wireless technology leader in Markham is seeking an ASIC verification engineer. The role involves verifying multimedia and compute ASIC modules, developing testbench components, and optimizing verification processes. Candidates should have at least 2 years in ASIC design verification and experience with Verilog/System Verilog. The position offers a pay range of $104,900 - $154,900. An accommodating workplace for individuals with disabilities is also emphasized.

Benefits

Equal opportunity employer

Accessible workplace

Qualifications

• 2+ years in ASIC design verification.
• Proven experience verifying Verilog and/or System Verilog RTL designs.
• Bachelor's, Master's, or PhD in related field.

Responsibilities

• Verify and model multimedia and compute ASIC modules.
• Develop reusable testbench components using System Verilog/UVM.
• Optimize verification methodology and automation using scripts.

Skills

ASIC design verification

Verilog/System Verilog RTL verification

Testbench components development

Functional model development

Verification automation using Python or PERL

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

System Verilog

UVM

VCS

Verdi

Questa

Xcelium

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm enables a world where everyone and everything can be intelligently connected. As the world's leading wireless tech innovator, we push the boundaries of what's possible to enable next‑gen experiences and drive digital transformation to help create a smarter, connected future for all. Our roadmap of breakthrough technologies expands our mobile innovations and solutions to support virtually every connected device. With our leadership in wireless connectivity, high‑performance, low‑power computing, and on‑device AI, we’re powering the connected intelligent edge. We are searching for an ASIC verification engineer interested in developing world‑class solutions for the next generation of AI/ML and video processing IP.

Principal Duties:

• Verification and modelling of multimedia and compute ASIC modules and sub‑systems
• Verify features and performance of IP‑level RTL using coverage‑driven, constrained‑random methodologies in System Verilog (i.e. UVM/OVM)
• Create comprehensive verification plans to describe the functional/feature test points of the DUT, and present the plan to the IP team
• Develop reusable testbench components such as scoreboards, reference models, checkers, drivers, monitors, and VIPs using SystemVerilog/UVM and C/C++
• Create functional coverage models to track the IP verification quality relative to the DV plan
• Develop SVA assertions for functional and formal verification
• Optimize coverage and test platform delivery processes using AI toolsets
• Implement verification methodology and automation using scripts (e.g. Python, Perl)
• Create performance verification monitors, models, and test scenarios
• Develop and support a regression and coverage flow to ensure high DV quality

Preferred Qualifications:

• 2+ years in ASIC design verification
• Proven experience verifying Verilog and/or System Verilog RTL designs
• Working experience using testbench components such as Interface VIPs, reference models, scoreboards, transactors
• Experience with several of the following tools/techniques
  • Functional model development (UVM, SystemC, SVAs, and/or C++)
  • Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
  • Design rule and Multi-frequency and CDC verification (SVA assertions)
  • Bus implementation/verification techniques
  • Verification automation using Python, PERL, or other scripting languages
• Practiced verification of one or more of the following
  • Data and/or image processing pipelines
  • Cache controllers
  • Clock domain crossing and Reset architecture
  • Bus interface protocols (APB, AHB, AXI) and RTL
  • FIFOs and memory controllers

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

Pay range and Other Compensation & Benefits:

$104,900.00 - $154,900.00

If you would like more information about this role, please contact Qualcomm Careers.