Senior ASIC Verification Designer

Fidus Systems; Ottawa; On-site; CAD 90,000 - 120,000; Full time

Job summary

A high-tech design firm headquartered in Ottawa is seeking a Senior ASIC Verification Engineer to lead complex verification projects for ASICs. This role requires expertise in creating UVM-based environments and drafting test plans, as well as 8+ years of experience in ASIC verification. Ideal candidates will possess strong problem-solving skills and the ability to collaborate with internal teams and clients. This position offers a chance to work with cutting-edge technology and a generous benefits package.

Benefits

Generous benefits package

Healthy work/life balance

Cultural emphasis on inclusivity

Qualifications

• 8+ years experience in ASIC verification including test-plan creation.
• Proven experience in leading verification projects.
• Strong proficiency in SystemVerilog, Verilog, and UVM.

Responsibilities

• Develop and execute test plans to validate ASIC blocks.
• Design UVM-based verification environments.
• Automate verification tasks with scripts.

Skills

UVM-based environments

SystemVerilog

Constrained random techniques

Debugging skills

Analytical skills

Interpersonal skills

Education

Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field

Tools

Verification methodologies

Job description

Headquartered in Ottawa, with additional design centers in Waterloo and San Jose, Fidus is a global leader and dynamic high‑tech design firm. Fidus specializes in leading‑edge electronic product development, integrating hardware, software, FPGA, and signal‑integrity expertise to innovate next‑generation solutions for clients across emerging technology markets.

Fidus delivers system, hardware, and embedded software design, providing a technical advantage to global clients from tech giants to start‑ups. Work spans high‑speed communication, high‑resolution video, and high‑performance computing.

Founded in 2001, Fidus has closed more than 4,000 projects for over 400 customers spanning telecom, aerospace, consumer, semiconductor, industrial‑automotive and medical industries. As a Premier Adaptive Computing Partner for AMD North America, Fidus employs in‑house expertise and industry‑leading tools to architect, design, and deliver land‑cutting solutions and tackle tough design challenges.

We are seeking a Senior ASIC Verification Engineer to lead and execute complex verification projects for ASICs. Ideal candidates possess extensive experience in drafting verification test plans, building UVM‑based environments, and steering verification methodologies to assure high‑quality designs. This role demands deep technical expertise, leadership ability, and strong collaboration with internal teams and external clients.

What’s in it for You?

• Working with a proudly Tier‑1 high‑tech design house at a rapidly expanding industry: Fidus offers full end‑to‑end development solutions or focused engagements. As an AMD Premier Adaptive Partner it has delivered 4,000+ projects for 400+ clients, from Tier‑1 to SMEs. Fidus evaluates and implements new technologies—often before release to marketplace.
• Join an evolving company: Influence change, drive growth in product road‑maps, contribute to challenging projects, and see your voice impact product and service evolution.
• Join during rapid‑growth mode: Hit a period of past‑year target achievements, secure projections, and build lasting client relationships based on integrity, quality, and open communication.
• Work with cutting‑edge technology: Fidus tackles hardware, software, and FPGA/ASIC design and verification. Project variety spans leading technologies, training, mentoring, and exposure to diverse teams and clients—builds early‑stage expertise.
• Generous benefits package and company culture: Full benefits, healthy work/life balance, LTD & STD, generous PTO, and cultural emphasis on welcoming everyone at home.

Responsibilities

• Develop and execute block‑level and system‑level test plans to validate ASIC blocks and subsystems.
• Design and implement UVM‑based verification environments and ensure compliance with best practices.
• Create behavioral models and write constrained random test cases to hit functional coverage goals.
• Apply formal verification techniques and assertions to improve verification efficiency.
• Debug and troubleshoot failures in simulation and regression runs, working with designers and architects.
• Define and track functional coverage metrics to ensure coverage completion and validate design specifications.
• Automate routine tasks with scripts to improve efficiency and monitor regressions.
• Own verification activities, including planning, monitoring progress, and reporting.
• Collaborate with external clients to deliver verification solutions and support.

Requirements

• 8+ years experience in ASIC verification, including test‑plan creation, environment setup, and test‑case writing.
• Proven verification lead experience, planning and delivering complex projects.
• Expertise in UVM‑based environments and constrained‑random techniques.
• Strong proficiency in SystemVerilog, Verilog, and UVM methodologies.
• Experience with functional coverage, assertions, and formal verification.
• Strong debugging, problem‑solving, and analytical skills.
• Familiarity with industry‑standard protocols such as Ethernet, DDR/LPDDR, HBM, AXI, NOC, ARM CPU subsystems.
• Automation of verification tasks via scripting languages.
• Excellent interpersonal, teamwork, and communication skills.
• Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.

This is an excellent chance to contribute to cutting‑edge ASIC designs, tackle industry‑leading verification projects, and work with a dynamic team. If you are passionate and have the skills to steer complex projects to completion, we welcome your application!

Fidus is committed to creating a diverse environment and is a proud equal‑opportunity employer.