ASIC Verification Engineer — SystemVerilog/UVM Pro

High Tech Genesis Inc.; Ottawa; On-site; CAD 70,000 - 90,000; Full time

Job summary

A leading design services company in Ottawa is seeking a Verification Engineer to push technological boundaries. The ideal candidate has experience in System Verilog, UVM, and programming skills in C and Python. You will develop verification plans, create testbenches, and collaborate with systems engineers. This position offers a dynamic work environment within a diverse team committed to innovation.

Qualifications

• Experience in using System Verilog.
• Experience in using UVM.
• Experience in programming languages: C and Python.
• Must have excellent problem-solving skills.

Responsibilities

• Read and understand architecture and requirements.
• Validate architectural functional blocks using various methods.
• Develop test plans and create testbench environments.
• Perform coverage-driven verification and debug failures.
• Provide regular updates on verification progress.

Skills

System Verilog

UVM

C

Python

Problem-solving

Job description

A leading design services company in Ottawa is seeking a Verification Engineer to push technological boundaries. The ideal candidate has experience in System Verilog, UVM, and programming skills in C and Python. You will develop verification plans, create testbenches, and collaborate with systems engineers. This position offers a dynamic work environment within a diverse team committed to innovation.