Senior RTL Design Engineer for AI Memory ASIC

TETRAMEM SINGAPORE PTE. LTD.; Singapore; On-site; SGD 100,000 - 125,000; Full time

Job summary

A semiconductor company in Singapore is looking for engineers to join their world-class IC design team. The role involves leading RTL design, integrating IP blocks, and optimizing designs for AI processing, with a strong emphasis on digital design methodologies. Candidates should have a master's or PhD in Electrical Engineering, with experience in Verilog and digital design tools. The company offers a competitive compensation package and benefits including insurance and paid time off.

Benefits

Insurance

Paid time off

Full benefits package

Qualifications

• 4+ years experience in RTL/SoC/digital design required.
• Familiarity with FPGA/ASIC design considered a strong plus.
• Ability to work in a startup environment and provide technical leadership.

Responsibilities

• Lead RTL design, simulation, and verification efforts.
• Integrate and validate IP blocks within the system.
• Conduct Power, Performance, and Area (PPA) analysis.

Skills

Verilog

System Verilog

RTL design

Digital design

Simulation tools (VCS, Verdi)

AMBA APB AXI Protocol

RISC/Arm architectures

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

VCS

Verdi

Job description

A semiconductor company in Singapore is looking for engineers to join their world-class IC design team. The role involves leading RTL design, integrating IP blocks, and optimizing designs for AI processing, with a strong emphasis on digital design methodologies. Candidates should have a master's or PhD in Electrical Engineering, with experience in Verilog and digital design tools. The company offers a competitive compensation package and benefits including insurance and paid time off.