Pre-Silicon Chip Verification Engineer (UVM/SystemVerilog)

CANAAN CREATIVE GLOBAL PTE. LTD.; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

A technology development company in Singapore is seeking a skilled engineer to perform chip verification for new product development. The ideal candidate will have a Master's degree in Electrical Engineering, Microelectronics, or a related field, alongside over 3 years of experience in Pre-Silicon verification. Proficiency in Verilog/System Verilog and solid knowledge of UVM methodology are essential. Strong scripting skills and bilingual abilities are preferred, contributing to successful project milestones including simulation verification and validation requirements.

Qualifications

• 3+ years of experience in Pre-Silicon verification.
• Solid knowledge of UVM methodology is a strong advantage.
• Proficiency in Verilog/System Verilog is essential.

Responsibilities

• Perform chip verification for new product development.
• Participate in IP- and system-level simulation verification.
• Develop and maintain UVM-based verification environments.

Skills

UVM methodology

Verilog/System Verilog

Scripting (Python, Perl, Tcl, Shell)

Bilingual communication

Education

M.S. in Electrical Engineering, Microelectronics, or related field

Job description

A technology development company in Singapore is seeking a skilled engineer to perform chip verification for new product development. The ideal candidate will have a Master's degree in Electrical Engineering, Microelectronics, or a related field, alongside over 3 years of experience in Pre-Silicon verification. Proficiency in Verilog/System Verilog and solid knowledge of UVM methodology are essential. Strong scripting skills and bilingual abilities are preferred, contributing to successful project milestones including simulation verification and validation requirements.