MTS Metrology and Inspection, ULP CMOS Advanced Packaging

GLOBALFOUNDRIES SINGAPORE PTE. LTD.; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A semiconductor manufacturing leader in Singapore seeks a metrology engineer to develop strategies and ensure quality in advanced packaging. The ideal candidate will have a Bachelor's degree in engineering and at least 7 years of related experience. Responsibilities include collaboration with engineering teams and analysis of measurement data. Strong communication skills are essential, alongside a solid understanding of semiconductor processes. This position may involve some travel to global facilities.

Qualifications

• Minimum of 7 years of experience in semiconductor product engineering or related fields.
• Demonstrated experience in packaging metrology and defect inspection methodologies.
• Ability to analyze trends from data reports and recommend corrective actions.

Responsibilities

• Develop and implement metrology capabilities for ULP CMOS product lines.
• Collaborate with module engineering teams to ensure quality compliance.
• Investigate control issues and establish appropriate monitoring strategies.

Skills

Packaging metrology techniques

Defect inspection techniques

Electrical parametric correlation to product yield

Communication skills

Teamwork in a global matrixed environment

Education

Bachelor’s degree in engineering or related technical field

Job description

Introduction

The ULP CMOS product team is looking to hire a metrology engineer to join our growing Advanced packaging team in our Singapore facility. Applicants for this position would be responsible for developing new metrology and measurement strategies providing technical know-how and creativity to ensure critical risks are covered in the advanced packaging, new features and new offerings on base technologies in FINFET and FDSOI from early process demonstrations through manufacturing transfer. Areas of focus could include developing and monitoring in-line inspection and measurements performance of the features we are developing for the advanced packaging support of the full ULP CMOS suite of products.

Essential Responsibilities

• Advanced packaging metrology engineer will develop and implement critical capabilities for enabling early feedback loops and quality compliance to technical requirements for technology nodes across the ULP CMOS product lines for multiple development opportunities.
• This role supports advanced packaging metrology capability enablement and requires strong partnership and collaboration with the broader SGP module engineering team and process integration to develop and monitor health of these programs.
• Investigate root cause of any control issues as well as establish appropriate control strategy and monitoring through the program early ramp.
• Work with internal and external metrology, measurements and inspection suppliers to maximize metrology feedback to the factory.
• Partner with yield characterization and co‑lead data analysis methodologies to determine yield limiters correlated to in‑line defectivity or measurements.
• Support process module engineering activities to improve cost, cycle time, and manufacturing readiness.
• Ensure methods and processes in place to monitor and quality control all technical requirements for device and advanced packaging structures being developed.
• Analyze various data, physical, electrical or defect reports to determine trends and recommend corrective actions.
• May require creation of presentations to provide occasional management or external customer updates.
• Work and collaborate with other projects and/or assignments as needed.

Other Responsibilities

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
• Travel <10% to other GlobalFoundries facilities may be necessary.

Required Qualifications

• Bachelor’s degree in engineering, Material science or related technical field.
• Minimum of 7 years of semiconductor product yield or test engineering, circuit design, process integration or process engineering experience.
• Strong candidates will have demonstrated experience in packaging metrology techniques, defect inspection techniques and methodologies, solid understanding of electrical parametric correlation to product yield, and good knowledge of semiconductor processing and process integration.
• Excellent verbal and written communication skills.
• Strong interpersonal skills and ability to work effectively within a global matrixed team or environment.
• Prior experience in developing, transferring, implementing, ramping and sustaining process technologies in early development through manufacturing ramp into production.
• Strong fundamental understanding of circuit design and test, solid state device physics, submicron FET architecture, and the implications of electrical characteristics and performance on yield and product behavior.
• Candidates must have capabilities in the design, execution, and analysis of experiments. Proven project management, peer leadership, and mentoring skills. Preferred Qualifications: Experience in advanced technology (45nm node or below) is strongly preferred.
• Experience in digital CMOS or analog circuit or test structure design, characterization, test/debug, yield enhancement and/or product engineering.
• Fluency in English Language – written & verbal.

Preferred Qualifications

• M.S. preferred.
• Experience in advanced packaging technology (45nm node or below) is highly preferred.
• Experience with advanced metrology and/or optical inspection is a benefit.