Memory Design Automation & Memory Modeling

MEDIATEK SINGAPORE PTE. LTD.; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

A leading technology company in Singapore is seeking a modeling engineer to develop behavioral, FPGA, timing, and DFT simulation models. The role involves creating and optimizing SRAM models for ASIC design flow, requiring strong skills in Verilog, scripting in Perl or Python, and familiarity with EDA tools like VCS and QuestaSim. This position seeks team players who can ensure model correctness and improve memory IP performance. Note that this ad is for future openings, not immediate hiring.

Qualifications

• Bachelor's degree in a relevant field is required.
• Good understanding of Verilog syntax is essential.
• Experience with EDA simulation tools is critical.

Responsibilities

• Develop and integrate automation code.
• Execute EDA tools from various vendors.
• Collaborate with different teams for model verifications.

Skills

Verilog syntax

Linux systems

Scripting in Perl or Python

EDA simulation tools

Liberty timing syntax

UPF

System Verilog

Education

Bachelor's degree in Electrical Engineering or related

Tools

VCS

Design Compiler

QuestaSim

PrimeTime

Fastscan

Job description

MediaTek’s Memory Design Automation team is looking for fresh talent to join us as a modeling engineer for the development of behavioral, FPGA, timing and DFT simulation models. The role will be required to create, debug and optimize SRAM models for ASIC design flow.

The candidate must be a team player, able to communicate clearly and concisely to deliver quality work on time.

About the team

The Mediatek’s Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness.

What you do

• Develop and integrate automation code into existing memory compilers to generate models meant for ASIC design flow.
• Develop automation flow and scripts with Perl or Python.
• Execute EDA tools from vendors such as Synopsys, Mentor to verify models’ correctness.
• Stay up to date with current modeling standards and development to improve models and flows for better memory IP performance.
• Work with memory design, compiler team and DFT team and tool vendors to resolve model issues and find solutions.

What you bring

• Must have a Bachelor’s degree or higher in Electrical Engineering, Electronics Engineering, or related.
• Experience in Linux systems will be a plus.
• Good understanding of verilog syntax and its various aspects, such as behavioral, RTL and synthesizable verilog is a must.
• Good understanding of liberty timing syntax.
• Good understanding of upf and system verilog.
• Knowledge and experience with EDA simulation tools such as VCS, NC is required.
• Experience with EDA tools will be helpful:
  • DTF: Logicvision, Tessent, Fastscan
  • Synthesis: Design compiler, Genus
  • Simulation tools: VCS, QuestaSim, NC
  • STA tools such as PrimeTime
• Good scripting and flow automation skills, in Perl or Python.
• A team player, meticulous, able to work and learn independently are important attributes for this job.

Location: One North, Singapore

Important Note

This advertisement is not for immediate hiring but is intended to identify suitable candidates for future openings in this position.