Lead Physical Design Engineer – Timing & Power

YOXIA PTE. LTD.; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

A leading technology firm in Singapore is seeking an experienced engineer to create timing constraints and perform Static Timing Analysis (STA). Candidates should hold a degree in Electrical/Electronic Engineering and have hands-on experience with Synopsys or Cadence tools. Strong TCL scripting skills, good collaboration, and communication abilities are also essential to collaborate with design and physical engineers. This role is critical for achieving timing closure and correctness in projects.

Qualifications

• Degree in Electrical/Electronic Engineering (bachelor’s or Master’s).
• Hands-on experience with Synopsys or Cadence tool suites.
• Strong TCL scripting skills: Python is a plus.
• Team player with the ability to work independently and meet deadlines.
• Good communication skills (written and verbal).

Responsibilities

• Create timing constraints for functional and test modes, working closely with design and DFT teams.
• Perform Static Timing Analysis (STA) and achieve timing closure.
• Write low-power intent files (CPF/UPF) and verify them using CLP/VCLP.
• Run logic equivalence checks to ensure correctness.
• Collaborate with physical design engineers to fix netlist and timing issues.

Skills

Hands-on experience with Synopsys or Cadence tool suites

Strong TCL scripting skills

Good communication skills

Education

Degree in Electrical/Electronic Engineering

Job description

A leading technology firm in Singapore is seeking an experienced engineer to create timing constraints and perform Static Timing Analysis (STA). Candidates should hold a degree in Electrical/Electronic Engineering and have hands-on experience with Synopsys or Cadence tools. Strong TCL scripting skills, good collaboration, and communication abilities are also essential to collaborate with design and physical engineers. This role is critical for achieving timing closure and correctness in projects.