DFT Engineer (Senior Position)

SUNLUNE (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 80,000 - 110,000; Full time

Job summary

A leading tech company in Singapore is seeking an experienced AI Chip DFT Engineer. The role involves leading the design and implementation of test architectures for advanced AI chip designs, ensuring efficient testing processes. Candidates should have 7-8 years of experience in DFT, with expertise in methodologies like Scan, Memory repair, and circuit design. Collaboration and problem-solving skills are essential, along with familiarity with DFT tools and scripting languages.

Qualifications

• 7-8 years of experience in DFT with proven expertise in chip-level design.
• Proficiency in DFT methodologies, including Scan and Memory repair.
• Experience with DFT tools and scripting languages required.

Responsibilities

• Lead the design of DFT architecture for testing circuits.
• Perform thorough functional verification and simulations.
• Develop high-coverage and low-cost test vectors.

Skills

DFT methodologies including Scan

Functional verification

Problem-solving skills

Collaboration with cross-functional teams

Education

Bachelor's degree in Electronics Engineering or related field

Advanced degree (Master's or Ph.D.)

Tools

TCL

Perl

Python

Job description

Overview

We are seeking an experienced AI Chip DFT (Design for Test) Engineer to lead the design and implementation of test architectures for our advanced AI chip designs, ensuring efficient and reliable testing processes. This role involves taking ownership of integrating DFT circuits (Scan, Mbit, Memory repair, Bscan), performing comprehensive simulations, developing high-quality test vectors, and actively contributing to yield improvement and fault analysis.

Responsibilities

• Lead the design of DFT architecture at the chip level, implementing testing circuits such as Scan, Mbit, Memory repair, and Bscan.
• Implement DFT circuits and integrate them into the chip, ensuring proper timing constraints for DFT mode convergence.
• Perform thorough functional verification, pre-simulation, post-simulation, and power simulation of DFT circuits. Troubleshoot and resolve issues effectively.
• Develop high-coverage, low-cost test vectors and validate them rigorously through simulation and timing analysis.
• Drive yield improvement efforts and lead fault analysis activities. Take ownership of testing SDC constraint files in testing modes and contribute significantly to timing and power convergence in the backend.

Qualifications

• Bachelor’s degree in Electronics Engineering, Computer Science, or a related field. Advanced degrees (Master’s or Ph.D.) are a plus.
• Minimum of 7-8 years of experience in DFT, with proven expertise in chip-level DFT architecture design, circuit insertion, and testing.
• Proficiency in DFT methodologies, including Scan, Mbit, Memory repair, and Bscan.
• Strong experience with functional verification and simulations (pre/post, power simulation).
• Demonstrated ability to develop efficient test vectors and perform thorough timing and simulation analysis.
• Familiarity with yield improvement and fault analysis processes.
• Experience with DFT tools and scripting languages (e.g., TCL, Perl, Python).
• Strong problem-solving skills, meticulous attention to detail, and the ability to collaborate effectively with cross-functional teams.