Senior DFT Design Engineer: SoC Test & Automation (Hybrid)

Capgemini Engineering; Vila Nova de Gaia; Hybrid; EUR 60,000 - 90,000; Full time

Benefits offered by this job

Health insurance

Hybrid work environment

Career growth programs

Training and certifications

International project exposure

Referral program

Job summary

Capgemini Engineering is seeking a Senior DFT Engineer in Porto to advance DFT strategies across complex SOC designs. You will implement scan strategies, JTAG/ATPG flows, and MBIST, collaborating with Physical Design and STA teams to meet timing closures.

The ideal candidate has 6+ years of DFT experience, strong scripting skills, and proficiency with leading EDA tools. Hybrid work and global project exposure are offered.

Qualifications

• 6+ years hands-on experience with DFT/test flows for large SOCs.
• Strong knowledge of JTAG, ATPG, MBIST/LBIST and IEEE 1500.
• Experience with major EDA tools: Synopsys DFT Compiler, Tetramax, Tessent, VCS, Modus/Encounter.
• RTL simulation, synthesis, Linting, CDC/RDC checks, STA and quality metrics a plus.
• Scripting in Perl/Tcl/Python.
• Excellent written and spoken English; strong communication in multicultural environments.

Responsibilities

• Implement DFT techniques across projects and validate patterns.
• Collaborate with Physical Design and STA teams to address timing constraints.
• Develop and optimize ATPG patterns to improve test coverage and efficiency.
• Verify DFT circuitry and interfaces; debug simulation and timing issues.
• Support silicon bring-up and debugging of test-related issues.
• Participate in technical reviews and improve DFT methodologies and flows.

Skills

DFT

ATPG

JTAG

MBIST/LBIST

Perl

Tcl

Python

English

Problem solving

Communication

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

Tetramax

Tessent

VCS

Modus/Encounter

Job description

Capgemini Engineering is seeking a Senior DFT Engineer in Porto to advance DFT strategies across complex SOC designs. You will implement scan strategies, JTAG/ATPG flows, and MBIST, collaborating with Physical Design and STA teams to meet timing closures.

The ideal candidate has 6+ years of DFT experience, strong scripting skills, and proficiency with leading EDA tools. Hybrid work and global project exposure are offered.