Senior RTL Engineer – Hybrid SoC Design & Tape-out

Capgemini Engineering; Fundão; Híbrido; EUR 55 000 - 75 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Hybrid work

Health and life insurance

Referral program with bonuses

Great office locations

Career growth programs

Training and certifications

Resumo da oferta

Capgemini Engineering Portugal is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out, delivering high-performance, power-efficient SoCs and coordinating with Verification, Synthesis, STA, and Physical Design teams.

The role offers a hybrid work model, international projects, and training opportunities to advance your career. Candidates should have 6+ years in RTL/ASIC design and strong Verilog/SystemVerilog/VHDL skills.

Qualificações

• Bachelor's or Master's in Electrical or Computer Engineering or related field.
• 6+ years in RTL/ASIC/SoC/VLSI design.
• Proficiency with Verilog, SystemVerilog, or VHDL.
• Experience with microarchitecture and complex digital design.
• Strong understanding of SoC integration and design methodologies.
• Experience with lint, CDC, and low power design methods.
• Knowledge of synthesis flows and STA.
• Familiarity with ARM, RISC-V, or x86 architectures.
• Programming/scripting ability: Python, Perl, or C.
• Strong problem-solving and communication skills.

Responsabilidades

• Perform feasibility studies to support system architecture and interface specification.
• Define and develop microarchitectures for complex digital blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Execute RTL quality checks, including Lint, CDC, and Low Power verification.
• Develop timing constraints and support synthesis and timing closure activities.
• Collaborate with Verification, Synthesis, STA, Physical Design, and DFT teams to meet targets.
• Support design bring-up, integration, and tape-out activities.
• Create and maintain automation scripts, design flows, and engineering tools.
• Participate in technical reviews and continuous improvement initiatives.

Conhecimentos

RTL/ASIC/SoC/VLSI design

Microarchitecture definition

SoC design methodologies

Lint/CDC/Low Power verification

Synthesis & STA

CPU architectures (ARM/RISC-V/x86)

Python/Perl/C scripting

Verification methodologies

Problem solving & communication

Formação académica

Bachelor's or Master's in Electrical/Computer Engineering

Ferramentas

Verilog

SystemVerilog

VHDL

Descrição da oferta de emprego

Capgemini Engineering Portugal is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out, delivering high-performance, power-efficient SoCs and coordinating with Verification, Synthesis, STA, and Physical Design teams.

The role offers a hybrid work model, international projects, and training opportunities to advance your career. Candidates should have 6+ years in RTL/ASIC design and strong Verilog/SystemVerilog/VHDL skills.