Senior DFT Engineer — Hybrid SoC Test Lead

Capgemini; Lisboa; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Health and life insurance

Hybrid work environment

Career growth programs

Training and certifications

International projects

Referral program with bonuses

Great office locations

Job summary

Capgemini Engineering is seeking a Senior DFT Engineer to implement and verify DFT solutions for complex SoCs. You will drive block/top-level DFT insertion, ATPG pattern development, and pattern validation.

You will collaborate with Physical Design and STA teams to address timing constraints, verify interfaces, and debug timing issues while contributing to continuous DFT methodology improvements. Hybrid work is offered.

Qualifications

• 6+ years hands-on DFT and test flows with commercial EDA tools for large/complex SOCs.
• Strong knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, scan compression, IEEE 1500, MBIST/LBIST.
• Experience with major EDA providers: Synopsys DFT Compiler, Tetramax, VCS, Tessent, Modus/Encounter.
• RTL simulation, synthesis, Linting, CDC/RDC checks, STA, DFT—advantageous.
• Proficient in Perl/Tcl/Python scripting.

Responsibilities

• Implement and verify DFT solutions across complex designs.
• Perform block-level/top-level DFT insertion and validation.
• Develop ATPG patterns and improve fault coverage.
• Verify DFT circuitry and interfaces; debug timing issues.
• Collaborate with Physical Design and STA teams for timing closure.

Skills

DFT techniques (JTAG, ATPG, yield)

RTL simulation

Scripting (Perl/Tcl/Python)

Problem solving

Communication

Multicultural environments

Test pattern optimization

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

Tetramax

VCS

Tessent

Modus/Encounter

Job description

Capgemini Engineering is seeking a Senior DFT Engineer to implement and verify DFT solutions for complex SoCs. You will drive block/top-level DFT insertion, ATPG pattern development, and pattern validation.

You will collaborate with Physical Design and STA teams to address timing constraints, verify interfaces, and debug timing issues while contributing to continuous DFT methodology improvements. Hybrid work is offered.