Senior RTL Engineer: SoC Design & Tape-out

Capgemini Engineering; Vila Nova de Gaia; Hybrid; EUR 45,000 - 65,000; Full time

Benefits offered by this job

Hybrid work

Health and life insurance

Referral bonuses

Training and certifications

International projects

Job summary

Capgemini Engineering in Porto, Portugal, is seeking a Senior RTL Engineer to lead digital design from architecture through tape-out for high-performance, power-efficient products.

You will work with cross-functional teams to define microarchitectures, implement RTL using Verilog/SystemVerilog/VHDL, and ensure timing closure and verification across Lint, CDC, and Low Power methods. Hybrid work environment with global project exposure.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of experience in RTL, ASIC, SoC, or VLSI design.
• Strong knowledge of Verilog, SystemVerilog, and/or VHDL.
• Proven experience in microarchitecture definition and complex digital design development.
• Solid understanding of SoC design methodologies and integration.
• Hands-on experience with Lint, CDC, and Low Power design methodologies.
• Good knowledge of synthesis flows and Static Timing Analysis (STA).
• Familiarity with CPU architectures and instruction sets such as ARM, RISC-V, or x86.
• Experience with scripting and programming languages such as Python, Perl, or C.
• Understanding of verification methodologies and design flows.
• Strong problem-solving skills and attention to detail.
• Excellent communication skills and ability to work effectively in multicultural and multidisciplinary environments.

Responsibilities

• Drive digital design activities from architecture to tape-out.
• Define and develop microarchitectures for complex blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Perform RTL quality checks: Lint, CDC, Low Power verification.
• Develop timing constraints; support synthesis and timing closure.
• Collaborate with Verification, Synthesis, STA, Physical Design, and DFT teams.
• Support design bring-up, integration, and tape-out activities.
• Create and maintain automation scripts and design flows.
• Participate in technical reviews and continuous improvement.

Skills

RTL design

ASIC/SoC/VLSI design

Verilog/SystemVerilog/VHDL

Microarchitecture definition

SoC integration

Lint/CDC/Low Power

Synthesis/STA

CPU architectures (ARM/RISC-V/x86)

Python/Perl/C

Communication skills

Multidisciplinary teamwork

Education

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Tools

EDA tools

Synthesis tools

Job description

Capgemini Engineering in Porto, Portugal, is seeking a Senior RTL Engineer to lead digital design from architecture through tape-out for high-performance, power-efficient products.

You will work with cross-functional teams to define microarchitectures, implement RTL using Verilog/SystemVerilog/VHDL, and ensure timing closure and verification across Lint, CDC, and Low Power methods. Hybrid work environment with global project exposure.