Senior DFT (Design for Test) Engineer

Capgemini; Lisboa; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Health and life insurance

Hybrid work environment

Career growth programs

Training and certifications

International projects

Referral program with bonuses

Great office locations

Job summary

Capgemini Engineering is seeking a Senior DFT Engineer to implement and verify DFT solutions for complex SoCs. You will drive block/top-level DFT insertion, ATPG pattern development, and pattern validation.

You will collaborate with Physical Design and STA teams to address timing constraints, verify interfaces, and debug timing issues while contributing to continuous DFT methodology improvements. Hybrid work is offered.

Qualifications

• 6+ years hands-on DFT and test flows with commercial EDA tools for large/complex SOCs.
• Strong knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, scan compression, IEEE 1500, MBIST/LBIST.
• Experience with major EDA providers: Synopsys DFT Compiler, Tetramax, VCS, Tessent, Modus/Encounter.
• RTL simulation, synthesis, Linting, CDC/RDC checks, STA, DFT—advantageous.
• Proficient in Perl/Tcl/Python scripting.

Responsibilities

• Implement and verify DFT solutions across complex designs.
• Perform block-level/top-level DFT insertion and validation.
• Develop ATPG patterns and improve fault coverage.
• Verify DFT circuitry and interfaces; debug timing issues.
• Collaborate with Physical Design and STA teams for timing closure.

Skills

DFT techniques (JTAG, ATPG, yield)

RTL simulation

Scripting (Perl/Tcl/Python)

Problem solving

Communication

Multicultural environments

Test pattern optimization

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

Tetramax

VCS

Tessent

Modus/Encounter

Job description

# Senior DFT (Design for Test) EngineerVNG - Cais Gaia, Fundão, Lisboa - ExpoApply for this job* Permanent* Experienced Professionals* Products & Systems Engineering* ID 581661-en\\_GB## CAPGEMINI ENGINEERINGAt Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.## YOUR ROLEAs a Senior DFT Engineer, you will be responsible for implementing and verifying Design-for-Test solutions across complex digital designs, ensuring high test coverage, efficient patterns, and robust silicon testability.In this role, you will:* Perform DFT implementation in line with established test methodologies for advanced process nodes.* Execute block-level and top-level DFT insertion, including scan compression, (i)JTAG, ATPG, pattern validation and simulation, MBIST, and LBIST.* Develop and validate ATPG patterns, driving improvements in test coverage and pattern efficiency.* Verify DFT circuitry and interfaces with other blocks and IPs, identifying and debugging simulation and timing issues.* Collaborate closely with Physical Design and STA teams to address DFT-related timing constraints and support timing closure.* Perform hierarchical test implementation and retargeting across complex SoC designs.* Debug and optimize key DFT quality metrics, including fault coverage and pattern efficiency.* Support silicon bring-up, diagnosis, and physical failure analysis, contributing to the identification and resolution of test-related issues.* Participate in technical reviews and contribute to the continuous improvement of DFT methodologies, flows, and automation.## YOUR PROFILE* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.* 6+ years of hands-on experience with DFT and test flows with commercial EDA tools for large and complex SOCs.* Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST.* Experience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax, VCS, Tessent and Modus/Encounter tool suite.* Experience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT, quality metrics is a plus.* Hands-on in Perl/Tcl/Python scripting.* Good command of English, both written and spoken.* Strong problem-solving skills and attention to detail.* Excellent communication skills and ability to work effectively in multicultural and multidisciplinary environments.## WHAT YOU’LL LOVE ABOUT WORKING HERE* Join a multicultural and inclusive team environment.* Enjoy a supportive atmosphere promoting work life balance.* Hybrid work.* Your career growth is central to our mission. Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.* Access valuable training and certifications in cutting edge technologies.* Engage in exciting national and international projects.* Health and life insurance.* Referral program with bonuses for talent recommendations.* Great office locations.## ABOUT CAPGEMINICapgemini is the business transformation partner for enterprises in the age of AI. We help organizations imagine and build an intelligent, sustainable future, combining AI, technology and human ingenuity to transform how they operate, innovate and grow. With unique end-to-end capabilities spanning strategy, technology, engineering and intelligent operations, we bring together deep industry expertise and market-leading capabilities in AI, cloud and data to turn ambition into measurable business outcomes at scale. Supported by a robust ecosystem of partners and nearly 60 years of expertise, Capgemini is a responsible and diverse global organization of over 410,000 team members in more than 50 countries.