Senior RTL Engineer – SoC Design for Performance

Capgemini Engineering; Porto; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Hybrid work

Health and life insurance

Referral program with bonuses

Great office locations

Job summary

Capgemini Engineering in Porto, Portugal, is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out, delivering high‑performance, power‑efficient SoCs. You will collaborate with Verification, Synthesis, STA, Physical Design and DFT teams, develop timing constraints, and build automation to improve development efficiency.

Requires 6+ years in RTL/ASIC/VLSI with Verilog/SystemVerilog/VHDL.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 6+ years of experience in RTL, ASIC, SoC, or VLSI design.
• Strong knowledge of Verilog, SystemVerilog, and/or VHDL.
• Proven experience in microarchitecture definition and complex digital design development.
• Solid understanding of SoC design methodologies and integration.
• Hands‑on experience with Lint, CDC, and Low Power design methodologies.
• Good knowledge of synthesis flows and Static Timing Analysis (STA).
• Familiarity with CPU architectures and instruction sets such as ARM, RISC‑V, or x86.
• Experience with scripting and programming languages such as Python, Perl, or C.
• Understanding of verification methodologies and design flows.
• Strong problem‑solving skills and attention to detail.
• Excellent communication skills and ability to work effectively in multicultural environments.

Responsibilities

• Perform feasibility studies to support system architecture definition, requirements analysis, and interface specification.
• Define and develop microarchitectures for complex digital blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Execute RTL quality checks, including Lint, CDC, and Low Power verification.
• Develop timing constraints and support synthesis and timing closure activities.
• Collaborate with Verification, Synthesis, STA, Physical Design, and DFT teams to meet targets.
• Support design bring‑up, integration, and tape‑out activities.
• Create and maintain automation scripts, design flows, and engineering tools to improve development efficiency.
• Participate in technical reviews and contribute to continuous improvement.

Skills

RTL design

ASIC/SoC

Verilog

SystemVerilog

VHDL

SoC integration

Python scripting

CPU architectures

STA knowledge

Lint/CDC

Low Power design

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Python

Perl

C

Job description

Capgemini Engineering in Porto, Portugal, is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out, delivering high‑performance, power‑efficient SoCs. You will collaborate with Verification, Synthesis, STA, Physical Design and DFT teams, develop timing constraints, and build automation to improve development efficiency.

Requires 6+ years in RTL/ASIC/VLSI with Verilog/SystemVerilog/VHDL.