Analog Layout Engineer - FinFET, Precision & Reliability

Capgemini; Vila Nova de Gaia; Hybrid; EUR 60,000 - 90,000; Full time

Benefits offered by this job

Hybrid work

Health and life insurance

Referral program with bonuses

Great office locations

Training and certifications

Job summary

Capgemini Engineering in Porto is seeking an experienced Analog Layout Engineer with strong FinFET expertise. You will design and optimize analog layouts, ensure DRC/LVS compliance, and collaborate with circuit designers to enhance performance and reliability.

Key tasks include EM/IR analysis, parasitic mitigation, and implementation of matching techniques. Flexibility for hybrid work and international projects is offered.

Qualifications

• Minimum 5 years of hands-on FinFET layout design for Analog IP development.
• Strong knowledge of LDE effects (WPE, STI, LOD) and mitigation strategies.
• Proficiency in Cadence Virtuoso, Calibre and PVS.
• Familiarity with parasitic extraction flows and correlation techniques.
• Understanding of reliability mechanisms (BTI, HCI) and guard-banding in layout.
• Experience with advanced-node design rules and color-aware layout.
• Knowledge of EM/IR verification methodologies and sign-off flows.
• Ability to automate layout tasks using SKILL or Python scripts.

Responsibilities

• Develop analog layouts for circuits such as amplifiers, references, bias blocks and data converters in FinFET nodes.
• Apply best practices for DRC/LVS closure, including advanced tips and tricks for efficient debugging.
• Perform EM/IR analysis and implement layout changes to meet reliability targets.
• Address parasitic effects through careful routing, shielding, and post-extraction corrections.
• Implement matching techniques (common-centroid, interdigitation, dummy devices) for precision circuits.
• Collaborate with circuit designers to optimize layout for performance and yield.
• Ensure compliance with color-aware routing and multi-patterning constraints (SADP/SAQP).

Skills

FinFET layout design

LDE effects

Cadence Virtuoso

Calibre

PVS

Parasitic extraction

Reliability mitigation (BTI, HCI)

Color-aware layout

EM/IR verification

SKILL scripting

Python scripting

Advanced-node design rules

Color-aware routing

Tools

Cadence Virtuoso

Calibre

PVS

Job description

Capgemini Engineering in Porto is seeking an experienced Analog Layout Engineer with strong FinFET expertise. You will design and optimize analog layouts, ensure DRC/LVS compliance, and collaborate with circuit designers to enhance performance and reliability.

Key tasks include EM/IR analysis, parasitic mitigation, and implementation of matching techniques. Flexibility for hybrid work and international projects is offered.