Secure RTL Design Engineer (SystemVerilog & UVM)

Synopsys Inc; Moreira; On-site; EUR 70,000 - 110,000; Full time

Job summary

Synopsys Inc. in Porto, Portugal, seeks an experienced RTL Designer for Security IP cores. You will design and verify high-assurance IP, translating security requirements into synthesizable hardware.

The role emphasizes SystemVerilog and UVM, collaboration across hardware and software teams, and rigorous verification to ensure production-ready IP in automotive, AI, and HPC applications.

Qualifications

• Solid RTL design experience with synthesizable Verilog/SystemVerilog.
• Experience in ASIC verification using SystemVerilog, UVM, or Verilog in real projects.
• Ability to map requirements to verification objectives with test environments.
• Advanced degree in EE/CS or related field.

Responsibilities

• Design and implement RTL in Verilog and SystemVerilog for Security IP cores.
• Build and maintain test environments for digital hardware Security IP using SystemVerilog and UVM.
• Verify IP cores and subsystems using UVM testbenches and formal verification tools.
• Collaborate with hardware and software security engineers to analyze correctness and performance.
• Contribute to design specs, verification plans, and documentation for global teams.
• Work in an international team across time zones, coordinating reviews and milestones.

Skills

RTL design

SystemVerilog

UVM

Debugging skills

Education

MSc or PhD in Electrical Engineering, Computer Science, or related

Tools

Verilog

SystemVerilog

UVM

Formal verification tools

Job description

Synopsys Inc. in Porto, Portugal, seeks an experienced RTL Designer for Security IP cores. You will design and verify high-assurance IP, translating security requirements into synthesizable hardware.

The role emphasizes SystemVerilog and UVM, collaboration across hardware and software teams, and rigorous verification to ensure production-ready IP in automotive, AI, and HPC applications.