Senior ASIC Verification Engineer — AI-Driven Testbenches

Synopsys, Inc.; Moreira; On-site; EUR 18,000 - 24,000; Part time

Job summary

Synopsys, Inc. is offering an entry-level verification-focused role in Porto, Portugal. You will learn to verify DisplayPort and HDMI IP using industry-standard tools, under mentorship from senior engineers who guide your development.

The role emphasizes learning UVM, SystemVerilog, and functional safety practices. You will contribute to test case development, run simulations, debug failures, and grow your verification skills within a global IP team.

Qualifications

• Bachelor's or Master's degree in Electronic Engineering, Computer Science or related field.
• Exposure to Verilog or SystemVerilog in academic projects is desirable.
• Familiarity with UVM and SystemVerilog is a plus.

Responsibilities

• Write test cases and develop UVM testbench components under guidance from senior engineers.
• Run simulations, analyze results, and document coverage progress.
• Debug simulation failures using waveforms and logs with team support.
• Help build agentic workflows for verification, including test planning and coverage analysis.
• Learn to apply SystemVerilog assertions and functional coverage techniques.
• Support functional safety verification activities for ISO 26262 compliance.

Skills

Team collaboration

Problem solving

English communication

Education

Bachelor's or Master's in Electronic Engineering / Computer Science

Tools

Verilog

VHDL

SystemVerilog

UVM

Unix

Scripting basics

Job description

Synopsys, Inc. is offering an entry-level verification-focused role in Porto, Portugal. You will learn to verify DisplayPort and HDMI IP using industry-standard tools, under mentorship from senior engineers who guide your development.

The role emphasizes learning UVM, SystemVerilog, and functional safety practices. You will contribute to test case development, run simulations, debug failures, and grow your verification skills within a global IP team.