Staff Digital Design Engineer — Security IP (RTL/Verilog)

Synopsys, Inc.; Moreira; Presencial; EUR 60 000 - 90 000; Tempo integral

Resumo da oferta

Synopsys, Inc. in Porto seeks an ASIC Digital Design Engineer with RTL expertise to develop and verify Security IP cores.

You will implement RTL in Verilog and SystemVerilog, build UVM-based test environments, and collaborate with security engineers to ensure robust threat-resilient IP. Ideal candidates have a MSc/PhD in engineering, 3+ years in RTL/ASIC design, and strong verification skills in SystemVerilog, UVM, and Verilog.

Qualificações

• MSc or PhD in Electrical Engineering or Computer Science.
• 3+ years of RTL design for hardware IP components with synthesizable SystemVerilog experience.
• Proficiency in ASIC verification using SystemVerilog, UVM, and/or Verilog.
• Ability to create detailed test environments specifications.
• Strong understanding of IC design flows and debugging skills.

Responsabilidades

• Design and implement RTL in Verilog and SystemVerilog for Security IP cores.
• Build and maintain test environments for digital hardware Security IP using SystemVerilog and UVM.
• Verify IP cores and subsystems using UVM testbenches and formal verification tools.
• Collaborate with hardware and software security engineers to evaluate correctness and performance.
• Contribute to design specs, verification plans, and documentation for global development and customer integration.
• Work with an international team across time zones and coordinate reviews and milestones.

Conhecimentos

RTL design

SystemVerilog

UVM

Verilog

ASIC verification

Security IP

Formação académica

MSc or PhD in Electrical Engineering or Computer Science

Ferramentas

SystemVerilog

UVM

Verilog

Descrição da oferta de emprego

Synopsys, Inc. in Porto seeks an ASIC Digital Design Engineer with RTL expertise to develop and verify Security IP cores.

You will implement RTL in Verilog and SystemVerilog, build UVM-based test environments, and collaborate with security engineers to ensure robust threat-resilient IP. Ideal candidates have a MSc/PhD in engineering, 3+ years in RTL/ASIC design, and strong verification skills in SystemVerilog, UVM, and Verilog.