Senior ASIC Verification Engineer - HBM & SystemVerilog

Synopsys, Inc.; Porto; Hybrid; EUR 55,000 - 85,000; Full time

Job summary

Synopsys, Inc. in Porto, Portugal seeks a highly skilled Verification Engineer to lead ASIC digital verification with HBM protocol expertise. You will design verification plans, build testbenches with SystemVerilog and UVM, and collaborate with design teams to meet specifications.

You will debug complex ASIC issues, optimize verification environments, and mentor junior engineers, contributing to high-performance silicon chip validation and overall product quality.

Qualifications

• Extensive ASIC digital verification experience with HBM protocols.
• Proficiency in SystemVerilog, UVM and verification methodologies.
• Strong understanding of digital design and verification processes.
• Experience with simulation and debugging techniques.

Responsibilities

• Develop and execute verification plans for ASIC designs.
• Create and maintain testbenches using SystemVerilog and UVM.
• Collaborate with design and architecture teams to interpret specs.
• Identify, isolate, and debug issues in complex ASICs.
• Enhance verification environments and test suites.
• Review design and verification documentation.
• Mentor and guide junior verification engineers.

Skills

SystemVerilog

UVM

ASIC verification

HBM protocols

Testbenches

Debugging

Simulation tools

Mentoring

Collaboration

Job description

Synopsys, Inc. in Porto, Portugal seeks a highly skilled Verification Engineer to lead ASIC digital verification with HBM protocol expertise. You will design verification plans, build testbenches with SystemVerilog and UVM, and collaborate with design teams to meet specifications.

You will debug complex ASIC issues, optimize verification environments, and mentor junior engineers, contributing to high-performance silicon chip validation and overall product quality.