Hybrid Senior Verification Engineer - Analog & SoC

Capgemini Engineering; Fundão; Hybrid; EUR 45,000 - 60,000; Full time

Benefits offered by this job

Hybrid work

Health and life insurance

Referral bonuses

Great office locations

Job summary

Capgemini Engineering is seeking Design Verification Engineers to join its Semiconductor team in Portugal. You will verify complex digital IPs and SoCs across advanced projects, from RTL to emulation, helping build robust DV processes and standards.

The role requires a degree in electrical/electronics/computer engineering with 4+ years experience, strong SystemVerilog and UVM/OVM, UVC experience, scripting skills, and a proactive, international mindset with fluent English.

Qualifications

• Degree in Electrical Engineering, Electronics, Computer Engineering, Microelectronics or a related field.
• +4y of experience.
• Sound knowledge of SystemVerilog, and good experience in Constrained Random and Coverage Driven Verification with UVM/OVM.
• Experience in creating any UVC components or sequences is a must.
• Basic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc.
• Should be comfortable in updating the existing verification environment for feature updates. (Bring-up/Architect UVM based Test bench from Scratch is a strong plus) EDA simulation/debugging tools agnostic.
• Good knowledge of Perl/TCL/Python scripting.
• Domain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile.
• Strong analytical and debugging skills, with the ability to collaborate effectively within multidisciplinary and international engineering teams.
• Fluent in English.

Responsibilities

• Own verification of IP’s and SoC’s in prototype and SoC design environment;
• Establish functional and performance benchmarks;
• Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms;
• IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.

Skills

SystemVerilog

UVM/OVM

UVC development

Perl scripting

Python scripting

English fluency

AXI/PCIe knowledge

Education

Electrical/ Electronics/ Computer Engineering degree

Tools

UVC tools

Job description

Capgemini Engineering is seeking Design Verification Engineers to join its Semiconductor team in Portugal. You will verify complex digital IPs and SoCs across advanced projects, from RTL to emulation, helping build robust DV processes and standards.

The role requires a degree in electrical/electronics/computer engineering with 4+ years experience, strong SystemVerilog and UVM/OVM, UVC experience, scripting skills, and a proactive, international mindset with fluent English.