Hybrid Design Verification Engineer for SoCs & IPs

Capgemini Engineering; Lisboa; Hybrid; EUR 42,000 - 60,000; Full time

Benefits offered by this job

Hybrid work

Career growth programs

Training & certifications

National & international projects

Health and life insurance

Referral bonuses

Great office locations

Job summary

Capgemini Engineering is seeking Design Verification Engineers to join our Semiconductor team in Portugal. You will verify complex digital IPs and SoCs, contribute to DV methodologies, and work across RTL to emulation environments in a collaborative, international setting.

The role requires a degree in a related engineering field, 4+ years of experience, SystemVerilog/UVM expertise, UVC experience, and strong scripting skills. Hybrid work and career growth opportunities are offered.

Qualifications

• Degree in Electrical Engineering or related field.
• +4 years of experience.
• SystemVerilog, UVM/OVM with constrained random and coverage-driven verification.
• Experience creating UVC components or sequences.
• Knowledge of at least two protocols (AHB/AXI, PCIe/CXL, USB, DDR, Serial); one protocol required for senior.
• Proficiency in Perl/TCL/Python scripting.

Responsibilities

• Verify IPs and SoCs in prototype and design environment.
• Establish functional and performance benchmarks.
• Lead the definition, execution, and improvement of a DV methodology and tool flow across platforms.
• DV of IP/SoC from RTL to emulation with functional performance.

Skills

Electrical Eng

4+ years exp

SystemVerilog/UVM

UVC components

Verification protocols

Perl/TCL/Python

Domain expertise (senior)

Fluent in English

Education

Engineering degree

Job description

Capgemini Engineering is seeking Design Verification Engineers to join our Semiconductor team in Portugal. You will verify complex digital IPs and SoCs, contribute to DV methodologies, and work across RTL to emulation environments in a collaborative, international setting.

The role requires a degree in a related engineering field, 4+ years of experience, SystemVerilog/UVM expertise, UVC experience, and strong scripting skills. Hybrid work and career growth opportunities are offered.