Security ASIC RTL Design Engineer for IP Cores

Synopsys Inc; Moreira; Vor Ort; EUR 60.000 - 90.000; Vollzeit

Zusammenfassung

Synopsys Porto is seeking an ASIC Digital Design Engineer focused on RTL design and security-conscious IP development. You will design and verify security IP cores, working with an international team across time zones.

Requirements include MSc/PhD in EE or CS and 3+ years in RTL design, SystemVerilog, and ASIC verification. Collaboration on security-driven IP is essential for this role.

Qualifikationen

• MSc or PhD in Electrical Engineering or Computer Science (or related).
• 3+ years of RTL design experience for hardware IP components with hands-on SystemVerilog.
• Ability to create detailed specifications for test environments.
• Proficiency in ASIC verification using SystemVerilog, UVM, and Verilog.
• Strong understanding of IC design flows and problem-solving skills.
• Experience with hardware security concepts or cryptographic IP is a plus.

Aufgaben

• Design and implement RTL in Verilog and SystemVerilog for Security IP cores.
• Build and maintain test environments for digital hardware Security IP using SystemVerilog and UVM.
• Verify IP cores and subsystems with modern verification techniques including UVM testbenches and formal verification tools.
• Collaborate with hardware and software security engineers to analyze functional correctness and performance.
• Contribute to detailed design specifications, verification plans, and documentation.
• Work within an international team across time zones, coordinating reviews and milestones.

Kenntnisse

RTL design

SystemVerilog

UVM

Verilog

Security IP

Ausbildung

MSc or PhD in Electrical Engineering

Tools

Formal verification tools

Jobbeschreibung

Synopsys Porto is seeking an ASIC Digital Design Engineer focused on RTL design and security-conscious IP development. You will design and verify security IP cores, working with an international team across time zones.

Requirements include MSc/PhD in EE or CS and 3+ years in RTL design, SystemVerilog, and ASIC verification. Collaboration on security-driven IP is essential for this role.