Senior ASIC Verification Engineer – Digital Design

Synopsys Inc; Moreira; On-site; EUR 55,000 - 75,000; Full time

Job summary

Synopsys Inc in Porto is seeking a highly skilled Verification Engineer to join our ASIC Digital Design team. You will drive verification activities for high‑performance silicon and collaborate with cross‑functional teams.

You will develop verification plans, create testbenches in SystemVerilog/UVM, isolate and fix issues, and mentor junior engineers while staying current with verification trends.

Qualifications

• Extensive experience in ASIC digital verification, including HBM protocols.
• Proficient in SystemVerilog, UVM, and verification methodologies.
• Strong debugging and problem-solving skills.

Responsibilities

• Developing and executing comprehensive verification plans for ASIC designs.
• Creating and maintaining testbenches using SystemVerilog and UVM methodologies.
• Collaborating with design and architecture teams to understand design specifications and requirements.
• Identifying, isolating, and debugging issues in complex ASIC designs.
• Implementing and optimizing verification environments and test suites.
• Reviewing and providing feedback on design and verification documentation.
• Mentoring and guiding junior verification engineers.

Skills

ASIC digital verification

HBM protocols

Tools

SystemVerilog

UVM

Job description

Synopsys Inc in Porto is seeking a highly skilled Verification Engineer to join our ASIC Digital Design team. You will drive verification activities for high‑performance silicon and collaborate with cross‑functional teams.

You will develop verification plans, create testbenches in SystemVerilog/UVM, isolate and fix issues, and mentor junior engineers while staying current with verification trends.