HDL Design/Verification Engineer (FPGA Simulation)

Lattice Semiconductor; Penang; On-site; MYR 90,000 - 120,000; Full time

Job summary

A leading technology company in Malaysia is seeking an experienced HDL design/verification engineer to design and enhance simulation capabilities in their FPGA design tool. The role involves enabling simulation workflows, resolving issues, and validating simulation features. Candidates should possess a degree in Electronics Engineering and have solid experience with HDLs and simulation tools, ideally for over 5 years. Competitive compensation and a collaborative team environment are offered.

Benefits

Competitive compensation

Comprehensive benefits

Technical mentorship

Qualifications

• Solid experience with hardware description languages (HDLs) and simulation tools.
• Strong understanding of HDL simulation concepts.
• Industrial experience in similar field for over 5 years.

Responsibilities

• Design, develop, and enhance simulation capabilities within Lattice Radiant.
• Enable and support simulation workflows across various Lattice FPGA families.
• Assist in diagnosing and resolving simulation issues.
• Validate and test simulation features and debug interfaces.

Skills

Hardware description languages (HDLs)

Simulation tools (e.g., Modelsim, Synopsis VCS)

Analysis and debugging capabilities

Communication and collaboration skills

Education

Bachelor’s or Master’s degree in Electronics Engineering or related field

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world‑class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results‑oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

We are seeking an experienced HDL design/verification engineer to design, develop, and enhance the simulation capabilities within Lattice Radiant — Lattice Semiconductor’s official FPGA design tool. You’ll be part of the Lattice Software Radiant team working closely with the hardware developers and QA teams to support simulation flows, help validate new features and ensure seamless integration of simulation engines with Radiant’s toolchain.

Key Responsibilities：

• Enable and support simulation workflows for Verilog, VHDL, and SystemVerilog across various Lattice FPGA families.
• Assist in diagnosing and resolving simulation issues reported by internal developers or users.
• Validate and test simulation features, waveform viewers, and debug interfaces within Radiant.
• Contribute to automation scripts and testbench generation tools.
• Maintain simulation documentation, troubleshooting guides, and user tutorials.

Required Qualification:

• Bachelor’s or Master’s degree in Electronics Engineering, or related field
• Solid experience with hardware description languages (HDLs) and simulation tools (e.g., Modelsim, Synopsis VCS)
• Solid understanding of HDL simulation concepts: elaboration, scheduling, waveform generation
• Solid experience in EDA tool development or FPGA simulation frameworks
• Familiarity with Lattice Radiant Software, FPGA architectures, and configuration flows
• Industrial experience in similar field for > 5 years.

Preferred Skillsets:

• Strong analysis and debugging capabilities.
• Excellent communication and cross-disciplinary collaboration skills.

What We Offer:

• Direct impact on the evolution of FPGA development tools and methodology.
• Competitive compensation and comprehensive benefits.
• A highly collaborative and intellectually driven team environment.
• Supportive cross‑geo team environment and technical mentorship.