Lead DRAM Layout Design Engineer — Mixed-Signal Focus

3050 Micron Semiconductor Mexico, S.de R.L. de C.V.; Jalisco; Vor Ort; MXN 600.000 - 800.000; Vollzeit

Zusammenfassung

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking a skilled layout engineer in Mexico, Jalisco. The role involves layout implementation, dissecting designs at the chip level, and developing methodologies for advanced DRAM products.

The ideal candidate must have over 5 years of experience in layout design, a BS/MS in Electrical or Computer Engineering, and proficiency in Cadence Virtuoso Suite. Strong problem-solving skills and effective communication are essential for collaboration with global teams.

Qualifikationen

• 5+ years of experience in layout design required.
• Strong knowledge in high-performance techniques.
• Ability to use Cadence Virtuoso Suite and LVS/DRC tools.

Aufgaben

• Implement layout and evaluate designs at the chip level.
• Develop mixed-signal layout methodologies for advanced DRAM.
• Collaborate with cross-functional teams to solve layout challenges.

Kenntnisse

Basic CMOS circuit design knowledge

5+ years in layout design

Strong fundamentals in high-performance techniques

Skilled in debugging and problem-solving

Effective communicator

Team player with leadership experience

Ausbildung

BS/MS in Electrical or Computer Engineering

Tools

Cadence Virtuoso Suite

LVS/DRC tools

Jobbeschreibung

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking a skilled layout engineer in Mexico, Jalisco. The role involves layout implementation, dissecting designs at the chip level, and developing methodologies for advanced DRAM products.

The ideal candidate must have over 5 years of experience in layout design, a BS/MS in Electrical or Computer Engineering, and proficiency in Cadence Virtuoso Suite. Strong problem-solving skills and effective communication are essential for collaboration with global teams.