Senior DRAM Layout Engineer — Advance Memory Tech

Micron Technology, Inc.; Tlaquepaque; On-site; MXN 1,653,000 - 2,387,000; Full time

Benefits offered by this job

Medical plans

Dental plans

Vision plans

Income protection

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Mexico is seeking a DRAM Layout Designer to translate schematics into physical layouts for fabrication reticles.

You will optimize IP layouts for DRAM products and collaborate with design, CAD, and global engineering teams to meet quality and timing targets. The role requires strong CMOS layout fundamentals, proficiency with Cadence Virtuoso and Mentor Calibre, and experience in physical verification tasks such as DRC/LVS.

Qualifications

• Bachelor's or Master's in Electronics Engineering, VLSI, Mechatronics, or related field.
• Experience developing custom layout designs in advanced CMOS tech with physical verification.
• Strong understanding of layout fundamentals including electromigration, IR drop, latch-up, parasitics, matching.
• Proficiency with Cadence Virtuoso and Mentor Calibre.
• Ability to collaborate with circuit designers, CAD teams, and cross-functional partners.

Responsibilities

• Develop and optimize IP layouts for DRAM products while ensuring compliance with design, process, and reliability requirements.
• Perform physical verification activities including DRC, LVS, EM, quality reviews, and documentation to support successful tape-out execution.
• Collaborate with design, CAD, and global engineering teams to solve layout challenges and drive project success.
• Guide and support team members through layout reviews, knowledge sharing, and technical problem-solving.
• Plan, communicate, and present layout strategies, progress, and results to stakeholders across worldwide teams.

Skills

Cadence Virtuoso

Layout design

DRC/LVS

EM analysis

IR drop

Parasitic analysis

Cross-functional collaboration

Education

Bachelor's or Master's in Electronics / VLSI

Tools

Mentor Calibre

Cadence tools

Job description

Micron Technology, Inc. in Mexico is seeking a DRAM Layout Designer to translate schematics into physical layouts for fabrication reticles.

You will optimize IP layouts for DRAM products and collaborate with design, CAD, and global engineering teams to meet quality and timing targets. The role requires strong CMOS layout fundamentals, proficiency with Cadence Virtuoso and Mentor Calibre, and experience in physical verification tasks such as DRC/LVS.