DRAM Layout Design Engineer – IP Layout & Verification Lead

3050 Micron Semiconductor Mexico, S.de R.L. de C.V.; Jalisco; Presencial; MXN 867.603 - 1.388.165; Jornada completa

Descripción de la vacante

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking a DRAM Design Engineer to transform schematics into layouts for fabrication reticules. Responsibilities include designing IP layouts, verifying layouts for quality, and ensuring timely project delivery.

The ideal candidate should have a Bachelor's in Electrical or Electronics Engineering and at least 3 years of experience in advanced CMOS layout design. Strong problem-solving skills and proficiency with Cadence tools are essential.

Formación

• 3+ years of experience in advanced CMOS layout designs.
• Excellent problem-solving skills related to power, performance, and verification.
• Proficiency in device matching and isolation techniques.

Responsabilidades

• Design and develop IP layouts for DRAM chips.
• Perform layout verification including LVS, DRC, and EM.
• Collaborate with global engineering teams to ensure project success.

Conocimientos

Layout design

Team collaboration

Problem solving

Expertise in layout optimization

Cadence tools

Educación

Bachelor's degree in Electrical/Electronics Engineering

Herramientas

Cadence Virtuoso

Mentor Calibre

Descripción del empleo

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking a DRAM Design Engineer to transform schematics into layouts for fabrication reticules. Responsibilities include designing IP layouts, verifying layouts for quality, and ensuring timely project delivery.

The ideal candidate should have a Bachelor's in Electrical or Electronics Engineering and at least 3 years of experience in advanced CMOS layout design. Strong problem-solving skills and proficiency with Cadence tools are essential.