Senior DRAM Layout Engineer - Tape-Out & CMOS Expert

3050 Micron Semiconductor Mexico, S.de R.L. de C.V.; Jalisco; On-site; MXN 600,000 - 900,000; Full time

Job summary

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking an experienced Layout Designer for DRAM products within Micron Technology’s organization. You will translate schematics into IP layouts and work with cross-functional teams to meet tape-out deadlines while ensuring design reliability.

The role requires strong CMOS layout knowledge, physical verification experience (DRC/LVS/EM), and proficiency with Cadence Virtuoso and Calibre in a global engineering environment.

Qualifications

• Bachelor's or master's degree in Electronics Engineering, VLSI Engineering, Mechatronics, or a related field.
• Experience in custom layout designs for advanced CMOS technologies with physical verification.
• Strong understanding of layout fundamentals: electromigration, IR drop, latch-up, parasitics, matching.
• Proficiency with Cadence Virtuoso and Mentor Calibre.
• Ability to collaborate with circuit designers, CAD teams, and cross-functional partners.

Responsibilities

• Develop and optimize IP layouts for DRAM products meeting design and reliability requirements.
• Perform physical verification (DRC, LVS, EM) and document results for tape-out.
• Collaborate with design, CAD, and global engineering teams to resolve layout challenges.
• Lead layout reviews and guide team members through technical problem-solving.

Skills

Layout optimization

Physical verification

Electromigration/IR drop analysis

Problem-solving

Cross-functional collaboration

Education

Bachelor's or Master's degree in Electronics Engineering, VLSI Engineering, Mechatronics, or a related field

Tools

Cadence Virtuoso

Mentor Calibre

Job description

3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking an experienced Layout Designer for DRAM products within Micron Technology’s organization. You will translate schematics into IP layouts and work with cross-functional teams to meet tape-out deadlines while ensuring design reliability.

The role requires strong CMOS layout knowledge, physical verification experience (DRC/LVS/EM), and proficiency with Cadence Virtuoso and Calibre in a global engineering environment.