DRAM Layout Engineer – Advanced CMOS & IP Design

Micron Technology, Inc.; Tlaquepaque; Sur place; MXN 700 000 - 1 000 000; Plein temps

Avantages offerts par ce poste

Medical, dental and vision plans

Paid time off

Paid holidays

Résumé du poste

Micron Technology, Inc. in Mexico seeks a Layout Engineer for DRAM design to translate schematics into physical layouts used to generate fabrication reticles.

You will apply digital and analog layout techniques while partnering with design, CAD, and engineering teams to meet product, process, quality, and schedule requirements. You will build expertise in advanced semiconductor processes, verification, mask generation, and tapeout while helping us innovate and improve layout methodologies.

Qualifications

• Bachelor's degree or equivalent in a technical field with EE foundation.
• Experience developing IP layouts using CMOS processes and physical verification.
• Proficiency in layout rules, routing, and reliability considerations.
• Ability to interpret schematics and evaluate layout impacts on performance and area.
• Experience with layout tools (Cadence Virtuoso) and physical verification (Calibre).

Responsabilités

• Develop and optimize IP layouts for DRAM products using digital/analog techniques.
• Perform LVS/DRC, EM analysis, and other verification tasks with quality checks.
• Plan layout activities, estimate effort, and ensure timely delivery.
• Collaborate with circuit designers, CAD teams, and global partners to resolve issues.
• Develop and improve layout methodologies and automation to boost efficiency.

Connaissances

CMOS layouts

Layout fundamentals

Electromigration

Device matching

Parasitic analysis

Crosstalk

IR drop

LVS/DRC

Formation

Electrical/ Electronics/ related engineering degree

Outils

Cadence Virtuoso

Siemens Calibre

Description du poste

Micron Technology, Inc. in Mexico seeks a Layout Engineer for DRAM design to translate schematics into physical layouts used to generate fabrication reticles.

You will apply digital and analog layout techniques while partnering with design, CAD, and engineering teams to meet product, process, quality, and schedule requirements. You will build expertise in advanced semiconductor processes, verification, mask generation, and tapeout while helping us innovate and improve layout methodologies.