Senior DRAM Layout Engineer – Tape-Out & Verification

Micron Technology, Inc.; Jalisco; On-site; MXN 1,004,000 - 1,451,000; Full time

Job summary

Micron Technology, Inc. in Mexico’s Jalisco region is seeking a DRAM DEG Layout Designer to translate schematics into physical layouts for fabrication tape-outs, coordinating with design and CAD teams to meet deadlines and ensure design integrity.

You will develop and optimize IP layouts for DRAM products, perform DRC/LVS/EM checks, and collaborate with global engineering teams to resolve layout challenges and deliver high-quality tape-outs.

Qualifications

• Bachelor’s or Master’s degree in Electronics Engineering, VLSI Engineering, Mechatronics, or a related field.
• Experience developing custom layout designs in advanced CMOS technologies with proficiency in physical verification methodologies.
• Strong understanding of layout fundamentals including electromigration, IR drop, latch-up, parasitic analysis, matching, shielding, coupling, and crosstalk effects.
• Proficiency with Cadence Virtuoso design environments and verification tools such as Mentor Calibre.
• Demonstrated problem-solving skills related to area optimization, power, performance, and layout quality.
• Ability to collaborate effectively with circuit designers, CAD teams, and cross-functional engineering partners.

Responsibilities

• Develop and optimize IP layouts for DRAM products while ensuring compliance with design, process, and reliability requirements.
• Perform physical verification activities including DRC, LVS, EM, quality reviews, and documentation to support successful tape-out execution.
• Collaborate with design, CAD, and global engineering teams to solve layout challenges and drive project success.
• Guide and support team members through layout reviews, knowledge sharing, and technical problem-solving.
• Plan, communicate, and present layout strategies, progress, and results to stakeholders across worldwide teams.

Skills

Layout fundamentals

Team collaboration

Problem solving

Education

Bachelor’s or Master’s degree in Electronics Engineering, VLSI Engineering, Mechatronics

Tools

Cadence Virtuoso

Mentor Calibre

Job description

Micron Technology, Inc. in Mexico’s Jalisco region is seeking a DRAM DEG Layout Designer to translate schematics into physical layouts for fabrication tape-outs, coordinating with design and CAD teams to meet deadlines and ensure design integrity.

You will develop and optimize IP layouts for DRAM products, perform DRC/LVS/EM checks, and collaborate with global engineering teams to resolve layout challenges and deliver high-quality tape-outs.