Layout Design Engineer — Analog & Mixed-Signal Focus

Micron Technology; Región Centro; On-site; MXN 600,000 - 900,000; Full time

Job summary

Micron Technology is seeking a Layout Build engineer for the DRAM Team in Guadalajara, Mexico. You will contribute to analog/mixed-signal layout and integration for high-performance memory applications in a global team.

With around 5 years of analog layout experience, you will use Cadence VLE/VXL and Mentor Calibre to ensure LVS/DRC quality and timely delivery of layouts across multiple projects. Strong collaboration and problem-solving skills are essential.

Qualifications

• Around 5 years of experience in analog/custom layout design in sophisticated CMOS process, in various technology nodes (Planar, FinFET).
• BE or MTech in Electronic/VLSI Engineering, or related.
• Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
• Hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.
• Knowledge of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)
• Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
• Ability to understand design constraints and implement high-quality layouts.

Responsibilities

• Build and development of analog, mixed-signal, custom digital block and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for timely delivery of block-level layouts with acceptable quality.
• Will bee leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment.
• Optimally copresentingith Global engineering teams to assure the success of layout project.

Skills

Analog layout

CMOS design

Problem solving

Teamwork

Communication

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Layout automation

Job description

Micron Technology is seeking a Layout Build engineer for the DRAM Team in Guadalajara, Mexico. You will contribute to analog/mixed-signal layout and integration for high-performance memory applications in a global team.

With around 5 years of analog layout experience, you will use Cadence VLE/VXL and Mentor Calibre to ensure LVS/DRC quality and timely delivery of layouts across multiple projects. Strong collaboration and problem-solving skills are essential.