DRAM IP Layout Engineer — Precision & Leadership

Micron Technology; Tlaquepaque; Presencial; MXN 1.041.124 - 1.388.165; Jornada completa

Descripción de la vacante

Micron Technology in Tlaquepaque, Jalisco seeks a skilled engineer to design and verify layouts for DRAM products. This role involves collaborating with global teams and leading layout projects to ensure timely delivery with high quality.

Candidates should have a strong foundation in Electronic/VLSI Engineering with at least 3 years of experience in advanced CMOS processes, excellent problem-solving skills, and proficient use of Cadence tools.

Formación

• 3+ years of experience in layout designs in advanced CMOS process.
• Expertise in layout area and routing optimization, design rules.
• Good understanding of layout fundamentals like Electro-migration and IR-drop.

Responsabilidades

• Responsible for Design and development of IP layouts for DRAM chips.
• Perform layout verification like LVS/DRC/EM, quality check.
• Guide and lead developing team members in their execution of layouts.

Conocimientos

Layout design

Problem-solving

Leadership

Communication

Educación

BE/BTech or MTech in Electronic/VLSI Engineering

Herramientas

Cadence tools

Virtuoso schematic editor

Mentor Calibre

Descripción del empleo

Micron Technology in Tlaquepaque, Jalisco seeks a skilled engineer to design and verify layouts for DRAM products. This role involves collaborating with global teams and leading layout projects to ensure timely delivery with high quality.

Candidates should have a strong foundation in Electronic/VLSI Engineering with at least 3 years of experience in advanced CMOS processes, excellent problem-solving skills, and proficient use of Cadence tools.