DRAM Layout Engineer – IP Layout & Verification

Micron Memory Malaysia Sdn Bhd; Tlaquepaque; Presencial; MXN 600.000 - 900.000; Jornada completa

Descripción de la vacante

Micron Technology, Inc. is seeking a DRAM Design Tech Layout Engineer in Tlaquepaque, Jalisco, Mexico.

You will translate schematics into layout suitable for fabrication reticles and work with Design and other engineering groups to apply various layout techniques for digital and analog circuits. Responsibilities include IP layout development, layout verification (LVS/DRC/EM), and ensuring on‑time delivery of high‑quality layouts.

Formación

• Experience in layout designs in advanced CMOS processes.
• Strong understanding of layout fundamentals and design rules.
• Experience with IP layout development and physical verification.

Responsabilidades

• Design and development of IP layouts for DRAM chips.
• Perform layout verification and quality checks (LVS/DRC/EM).
• Ensure on-time delivery of block-level layouts with quality.
• Guide and lead sub block layouts and review work.

Conocimientos

CMOS layout design

IP layout development

Layout verification (LVS/DRC/EM)

Cadence Virtuoso

Mentor Calibre

Device matching

Parasitic analysis

Team leadership

Cross‑functional collaboration

Educación

BE/BTech or MTech in Electronic/VLSI Engineering

Diploma in electronic or VLSI engineering (considered)

Herramientas

Cadence Virtuoso Layout

Mentor Calibre

Descripción del empleo

Micron Technology, Inc. is seeking a DRAM Design Tech Layout Engineer in Tlaquepaque, Jalisco, Mexico.

You will translate schematics into layout suitable for fabrication reticles and work with Design and other engineering groups to apply various layout techniques for digital and analog circuits. Responsibilities include IP layout development, layout verification (LVS/DRC/EM), and ensuring on‑time delivery of high‑quality layouts.