DRAM Layout Engineer: IP Block Design & Verification

Micron Technology; Jalisco; Presencial; MXN 480.000 - 720.000; Jornada completa

Descripción de la vacante

Micron Technology is seeking an experienced DRAM Layout Engineer to transform schematics into physical layouts for advanced CMOS processes. You will lead IP layout development, perform verification, and drive on-time delivery while coordinating with global teams across the US, India, and Japan.

Ideal candidates have 3+ years in CMOS layouts, strong Cadence skills, and a track record of collaborative leadership in multi-project environments.

Formación

• 3+ years of experience in layout designs in advanced CMOS process.
• Proficient in layout area, routing optimization, and design rules.
• Experience with IP layout development and physical verification.

Responsabilidades

• Design and develop IP layouts used in DRAM chips.
• Perform LVS/DRC/EM verification and documentation.
• Ensure on-time delivery of block-level layouts with quality.
• Lead and mentor team members in sub-block layouts and reviews.
• Coordinate with global engineering teams to ensure project success.

Conocimientos

Layout design

CMOS process

IP layout

Team leadership

Electrical verification

Educación

BE/BTech or MTech in Electronic/VLSI

Diploma in electronics/VLSI

Herramientas

Cadence Virtuoso

Mentor Calibre

Descripción del empleo

Micron Technology is seeking an experienced DRAM Layout Engineer to transform schematics into physical layouts for advanced CMOS processes. You will lead IP layout development, perform verification, and drive on-time delivery while coordinating with global teams across the US, India, and Japan.

Ideal candidates have 3+ years in CMOS layouts, strong Cadence skills, and a track record of collaborative leadership in multi-project environments.