We are seeking a highly skilled Senior Analog IC Design Engineer to lead our team in developing cutting-edge solutions for high-performance data communication. This role focuses on the design and development of high-speed Phase Locked Loop (PLL) circuits and integrated power management within advanced CMOS nodes.
The ideal candidate will have a proven track record in PLL and power management design, with experience working at or near 12nm nodes. A strong background in CMOS analog design fundamentals and proficiency in tools like Cadence and Spectre are also essential. Additionally, excellent problem-solving skills and attention to detail are required.
This is an excellent opportunity for a Senior Analog IC Design Engineer looking to work on novel technologies in a collaborative and forward-looking environment. The successful candidate will have the opportunity to bring their expertise and contribute to the development of next-generation solutions.
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