Senior Layout Designer

Analog Devices; Assago; In loco; EUR 60.000 - 80.000; Tempo pieno

Descrizione del lavoro

A leading semiconductor company in Italy is seeking a motivated Senior Layout Design Engineer to join their dynamic team. The role involves designing complex analog and mixed-signal layouts, collaborating with engineers for circuit optimization, and mentoring new talents. Ideal candidates will possess a Bachelor's degree in Electronics Engineering, along with at least 4 years of relevant experience. Proficiency in Cadence tools and a strong understanding of semiconductor physics are essential. This position may involve some travel.

Competenze

• Strong knowledge of semiconductor physics and advanced layout techniques.
• Experience managing complex projects and leading teams.
• Excellent written and verbal communication skills.

Mansioni

• Design analog / mixed‑signal layouts ensuring performance and quality.
• Collaborate closely with design engineers to optimize circuit performance.
• Mentor new colleagues and help improve layout methodologies.

Conoscenze

Semiconductor physics

Cadence Virtuoso Suite

Project management

Linux

Programming (C++, Python)

Formazione

Bachelor's degree in Electronics Engineering

Strumenti

Cadence tools

Calibre verification tools

Descrizione del lavoro

About Analog Devices

Analog Devices, Inc. is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.

Summary

We are looking for a motivated and ambitious Senior Layout Design Engineer to join our Milan-based team, part of the Power Solution Group within the Industrial BU. Our team supports Automotive Power design, focusing on Display, Lighting, and HV Power applications. You will work closely with schematic designers and layout teams worldwide, contributing to innovative products for the automotive sector.

Key Responsibilities

• Design analog / mixed‑signal layouts (BGAP, BIAS, ADC, DAC, LDO, OSC, AMP), ensuring performance and quality meet project requirements.
• Collaborate closely with design engineers to optimize circuit performance.
• Take the lead in developing macro‑blocks and top‑level layouts, including scheduling, floor‑planning, verification, and tape‑out.
• Mentor new colleagues and help improve layout methodologies.
• Troubleshoot issues and drive development initiatives within the group.

Technical Requirements

• Strong knowledge of semiconductor physics and advanced layout techniques.
• Excellent command of Cadence Virtuoso Suite (XL, analog router, etc.) and Calibre verification tools (LVS, DRC, ERC, ANT, PERC, Extraction, EM, etc.).
• Familiarity with best‑known layout practices: device matching, critical net shielding, EM, ESD, latch‑up, HV & powerFET layout, assembly constraints, multi‑well isolation.
• Experience managing complex projects and leading teams.

Education and Experience

• Bachelor’s degree in Electronics Engineering or equivalent.
• At least 4 years of relevant experience in the field.

Additional Skills

• Good knowledge of the Linux environment, data management, and archival tools.
• Programming experience (Cadence SKILL, C++, Python) is a plus.
• Ability to work effectively in multidisciplinary, multicultural, and distributed teams.
• Excellent written and verbal communication skills.
• Knowledge of digital implementation.

Job Req Type

Experienced, Required travel: Yes 10% of the time. Shift type: 1st Shift / Days.