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ASIC Design Engineer
Job summary
A leading technology company in the United Kingdom is seeking a Senior Digital Design Engineer to join their team. The role involves designing RTL with System Verilog and requires extensive experience in ASIC digital design. Ideal candidates have strong scripting skills and a solid understanding of implementation and verification front-end flows. Competitive salary and opportunity for professional growth are offered.
Qualifications
- Must have 8+ years of experience in ASIC Digital Design.
- Proficient in scripting languages like Python or Tcl.
- Familiar with RTL design best practices.
Responsibilities
- Design RTL with System Verilog for ASICs.
- Perform Linting checks with Spyglass.
- Conduct STA and synthesis processes.
Skills
Education
Senior Digital Design Engineer
We’re looking for a Senior ASIC Digital Design Engineer
Experience required
- RTL Design with System Verilog
- Linting checks with Spyglass
- STA
- Synthesis
- Experience with formal verification would be a plus
Key Qualifications
- BS/MS degree with a minimum of 8 years of related experience.
- Proficient in scripting languages (Python, Tcl, Perl, Unix shell)
- Familiar with RTL best design practices with SystemVerilog
- Familiar with implementation and verification front-end flows
- Strong communication skills
* The salary benchmark is based on the target salaries of market leaders in their relevant sectors. It is intended to serve as a guide to help Premium Members assess open positions and to help in salary negotiations. The salary benchmark is not provided directly by the company, which could be significantly higher or lower.