Senior/Principal Physical Design Engineer

Fractile; Greater London; On-site; GBP 80,000 - 110,000; Full time

Job summary

A leading AI technology firm in the UK is seeking a Senior/Principal Physical Design Engineer to spearhead the implementation of complex IC designs. The ideal candidate will have over 7 years of experience in physical design with strong proficiency in EDA tools. Responsibilities include driving ASIC/SoC implementations, collaborating with cross-functional teams, and addressing power optimization techniques. Join a dynamic team dedicated to shaping the future of AI and semiconductor technology in an innovative environment.

Qualifications

• 7+ years of experience in physical design for advanced technology nodes.
• Solid understanding of semiconductor physics and process limitations.
• Proficiency in timing closure and signal integrity analysis.

Responsibilities

• Drive physical implementation of ASIC/SoC designs.
• Collaborate with DFT engineers for design-for-test integration.
• Interface with foundries to ensure manufacturability.

Skills

Physical design implementation

Cross-functional collaboration

Power optimization

Tools proficiency (Cadence, Synopsys)

Scripting (TCL, Perl, Python)

Education

Bachelor's, Master's, or PhD in Electrical Engineering or related field

Tools

Cadence Innovus

Synopsys ICC2

Mentor Graphics Calibre

Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.

Preferred Qualifications

• Bachelor’, Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.