ASIC Digital Implementation Engineer

Synopsys, Inc.; Northampton; On-site; GBP 60,000 - 80,000; Full time

Job summary

A leading technology company in Northampton is seeking an experienced ASIC Digital Implementation Engineer. You will develop and implement methodologies for high-speed digital IP core designs and lead cross-functional collaborations. Ideal candidates have over 10 years of experience in ASIC design and proficiency with tools like Synopsys Fusion Compiler. Excellent communication skills and a passion for innovation are essential, along with a commitment to shaping advanced technological solutions in the industry.

Qualifications

• Over 10 years of hands-on experience in high-speed digital IP core and SOC development.
• In-depth knowledge of ASIC implementation and physical design flow.
• Direct experience with leading synthesis and place & route tools.

Responsibilities

• Develop front-to-back end design methodology using advanced tools.
• Collaborate with design teams to optimize Power, Performance, and Area.
• Enhance design processes for efficiency and innovation.

Skills

High-speed digital IP core development

Analytical problem-solving

Cross-functional collaboration

Excellent communication

Education

BS or MS in Electrical Engineering

Tools

Synopsys Fusion Compiler

Primetime

PrimePower

RLTA

CoreTools

Job description

Responsibilities

• Developing a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' advanced tools and technologies.
• Collaborating with industry-leading design teams to achieve best-in-class Power, Performance, and Area (PPA) for IP designs.
• Evaluating and optimizing all aspects of the ASIC development flow, including design for test logic, synthesis, place & route, and timing/power (EM/IR) analysis.
• Creating and maintaining digital design methodologies, including comprehensive documentation, scripting, and training resources.
• Acting as a liaison between EDA tool teams and IP design teams, ensuring seamless communication and workflow integration.
• Continuously refining and enhancing design processes to drive efficiency, scalability, and innovative outcomes.

The Impact You Will Have

• Drive innovation in the development of high-speed digital IP cores and subsystems.
• Enhance the efficiency and effectiveness of design and verification processes across global teams.
• Contribute to the creation of state-of-the-art technologies powering the next generation of intelligent systems.
• Ensure the highest quality standards in digital design and implementation, influencing final product excellence.
• Facilitate seamless global collaboration, fostering a culture of continuous learning and innovation.
• Advance Synopsys' leadership in ASIC design methodology, keeping the organization at the forefront of industry trends.

About You

You are an accomplished ASIC Digital Implementation Engineer with a proven track record-over a decade-of developing high-speed digital IP cores and/or SOCs. Your expertise encompasses the full spectrum of ASIC design flow, from RTL to GDSII, and you are highly proficient in leading Synthesis and Place & Route tools, such as Synopsys Fusion Compiler. You possess in-depth knowledge of IP deliverables, physical design methodologies, and complex digital architectures, including memories, logic libraries, and PDKs.

Your technical acumen is matched by your collaborative spirit. You excel at working with cross-functional, globally distributed teams, fostering innovation and driving collective success. Your communication skills-both written and verbal-are exemplary, enabling you to produce clear documentation and deliver effective training. You have a knack for problem-solving, always approaching challenges analytically and systematically to deliver robust, high-quality solutions. Familiarity with industry protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a strong asset, as is hands‑on experience with other Synopsys tools like Primetime, PrimePower, RLTA, and CoreTools. You are committed to continuous improvement-both your own and that of your team and processes-staying ahead in a rapidly evolving technological landscape. Above all, you are passionate about transforming ideas into reality and shaping the next generation of intelligent systems.

• BS or MS in Electrical Engineering or related discipline, with 10+ years of hands‑on experience in high-speed digital IP core and/or SOC development.
• In-depth knowledge of ASIC implementation, physical design flow, and associated tools, including memories, logic libraries, and PDK management.
• Direct experience with Synopsys Fusion Compiler or equivalent industry Synthesis and Place & Route tools.
• Proven ability to lead and facilitate cross-functional collaboration, driving innovation and delivering results.
• Strong analytical, debugging, and problem-solving skills, with a keen eye for detail.
• Excellent written and verbal communication skills, with experience creating clear documentation and delivering technical training.
• Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) and high-speed interface protocols (HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, DDR) is a plus.

Who You Are

• A collaborative team player who thrives in a fast-paced, dynamic environment.
• Innovative and proactive, always seeking ways to improve processes and outcomes.
• Effective communicator, able to articulate complex ideas to both technical and non-technical audiences.
• Resilient and adaptable, eager to tackle new challenges and learn emerging technologies.
• Detail-oriented with a strong commitment to quality and continuous improvement.

About the Team

You will join the Interface IP Digital Design Methodology team, a diverse and global group dedicated to defining best-in-class ASIC design standards and flows. The team partners closely with IP development groups and is at the forefront of innovation in next-generation SerDes and Memory interface controllers, PHYs, and subsystems. Together, you'll foster a culture of technical excellence, collaboration, and continuous learning.