Senior Analog Layout Engineer

Sofics; Köln; Hybrid; EUR 70.000 - 90.000; Vollzeit

Zusammenfassung

A leading semiconductor company in Germany is seeking an experienced Senior Analog Layout Engineer to design and integrate complex analog circuits. This role involves end-to-end schematic-to-layout design, physical verification, and collaboration with circuit design teams. The ideal candidate has over 8 years of experience in analog layout and a strong understanding of relevant tools and concepts. We offer a competitive salary and a flexible work environment.

Leistungen

Competitive salary package

Continuous learning opportunities

Flexible work environment

Qualifikationen

• 8+ years of hands-on experience in analog/mixed-signal IC layout.
• Proven expertise with layout and verification tools.
• In-depth knowledge of Layout-Dependent Effects and reliability considerations.

Aufgaben

• Execute end-to-end schematic-to-layout design for analog and GPIO circuits.
• Conduct full physical verification and ensure compliance with standards.
• Collaborate with circuit design teams for layout correlation and simulation feedback.

Kenntnisse

Analog layout fundamentals

Communication skills

Problem-solving skills

Python/Tcl scripting

Ausbildung

Bachelor’s or Master’s degree in Microelectronics or IC Design

Tools

Tanner

Cadence Virtuoso

Calibre

Jobbeschreibung

We are seeking an experienced Senior Analog Layout Engineer to design and integrate complex analog and GPIO circuits for advanced process technologies (e.g., TSMC 16nm and below) as well as deep sub-micron nodes. As part of our innovative research team, you will take full ownership of schematic-to-layout implementation, top-level integration, and layout sign-off-ensuring best-in-class performance, reliability, and manufacturability. This role requires close collaboration with analog design, PDK, and EDA tool teams to deliver robust, high-quality layouts that meet stringent foundry and reliability standards.

Key responsibilities

• Execute end-to-endschematic-to-layoutdesign for analog and GPIO circuits.
• Performfloor planning, IO pad-ring design,ESDimplementation, andtop-level integration.
• Conduct fullphysical verification(DRC, LVS, Antenna, Density, ERC, EMIR & PEX) and ensure compliance with foundry and reliability standards.
• Optimize layout formatching, symmetry, shielding, and parasitic controlto achieve superior performance and yield.
• Collaborate with circuit design teams forlayout correlation, simulation feedback, and sign-off support.
• Document layout methodologies, checklists, and best practices; contribute tolayout automationand process improvement.
• Participate incross-functional reviewsto maintain high-quality standards and continuous improvement.

Job profile

• Bachelor’s or Master’sdegree inMicroelectronics, IC Designor equivalent.
• 8+ yearsof hands-on experience inanalog/mixed-signal IC layoutfor advanced FinFET and CMOS technologies.
• Proven expertise withTanner, Cadence Virtuoso, and Calibretools for layout and verification environments.
• Strong understanding ofPCELLS/pycells,PDK Components,floor planning, power grid, IO ring, and ESD integration.
• In-depth knowledge ofLayout-Dependent Effects (LDE), EM/IR analysis, and reliability considerations.
• Solid grasp ofanalog layout fundamentals—including matching, shielding, low-noise design, and electromigration constraints.
• Ability to work bothindependently and as a team player, managing multiple deliverables and coordinating effectively with project leads.
• Excellentcommunication, problem-solving, and documentationskills.
• Python/Tclscripting knowledge is a plus.
• Fluency inEnglish or Dutch(written and spoken).
• Willingness to relocate within commuting distance (our location isAalter, Belgium).

Offer

You will join an SME with an extensive international customer base, healthy finances and strong growth potential. We offer a competitive and attractive salary package with various fringe benefits; we offer the opportunity for continuous learning, both through external and internal training. You will become part of our dynamic engineering team and work with top semiconductor companies worldwide.

We offer the flexibility of a start-up, the stability of an established, profitable and robust company, with facilities and benefits that match or exceed any other opportunity in our industry.

Because we value this, we operate out of a self-designed BEN (nearly energy neutral, an official label) building with spacious workstations, state-of-the-art lab and pleasant rest and meeting spaces. We also facilitate a personalized mix of office and home work.

Contract

How to Apply

Eager to contribute to the next wave of micro and nano semiconductor innovations? We want to hear from you! Send us your CV along with your interests [e-mail] .

At Sofics, we’re not just growing; we’re thriving, thanks to talents like you. Join us, and let’s create lasting value together.