Principal Engineer Digital Verification (f/m/div)

Infineon Technologies AG; München; Vor Ort; EUR 70.000 - 100.000; Vollzeit

Zusammenfassung

A leading semiconductor solutions provider in Munich seeks a Principal Engineer Digital Verification to spearhead the development of System Verilog - UVM testbenches. You will be responsible for defining functional coverage models, debugging complex issues, and enhancing verification strategies in a supportive environment. The ideal candidate will have over 6 years of verification experience, strong knowledge of UVM and System Verilog, and excellent leadership skills.

Leistungen

Diversity and Inclusion initiatives

Opportunities for career growth

Qualifikationen

• More than 6 years of experience in verification, preferably at the IP level.
• Advanced knowledge in UVM and SVAs, System Verilog.
• Experience with verification platform and framework development.

Aufgaben

• Develop System Verilog - UVM testbench and solve complex problems.
• Lead the development of new SV UVM verification components.
• Understand and modify Specman-e test benches.

Kenntnisse

System Verilog - UVM

Leadership skills

Time management

Programming and scripting

Ausbildung

Degree in Electrical Engineering or similar field

Tools

EDAD tools for simulation and emulation

Verification platform

Jobbeschreibung

Ready to lead in IP-level verification? Join us to develop advanced System Verilog-UVM testbenches, debug complex issues, and define functional coverage models. Collaborate with a passionate team, own end-to-end verification, and contribute to innovation in a supportive and dynamic environment!

Job Description

In your new role you will:

• Be responsible for developing System Verilog - UVM testbench and solve potentially complex problems related to test bench development for automotive algorithmic intense IPs such as graphics or security
• Be responsible and lead developing of new SV UVM verification components
• Able to understand and modify Specman-e test benches
• Debug failing test cases to root cause
• Be responsible for defining and writing a functional coverage model
• Participate in reviews to ensure the test bench meets quality and is complete
• Contribute to verification perspective in Design and Concept meetings
• Ensure the test bench meets sign-off targets, including coverage, functional safety, and test bench qualification
• Develop a deep understanding of complex IPs and take end-to-end ownership of the verification of these sub-blocks
• Proactively help increase the efficiency of verification activities and mitigate risks early
• Contribute to enhancing the Verification strategy and architecture of IP test benches

Your Profile
As a Principal Engineer Digital Verification, you concentrate your creativity and knowledge on producing results with real added value. Lastly, you clarify areas of responsibility, coordinate your work with colleagues, and regularly share your insights with them.

You are best equipped for this task if you have:

• A degree in Electrical Engineering or a similar field
• At least more than 6 years of experience working in Verification, preferably at the IP level, with System Verilog – UVM. Prior knowledge in Specman-e is desirable
• Advanced knowledge in UVM and SVAs, System Verilog
• Applied knowledge in programming and scripting
• Experience with Verification platform and framework development
• Proven experience of ownership of IP verification including delivering to metric targets
• Capability to understand complex Design specification, derive features and test bench architectures from concept
• Capability to use industry-standard EDA tools for simulation and emulation
• Good time management skills and the ability to deliver to high quality requirements under pressure
• Aptitude for clear communication of issues and progress
• A safety-first approach with ability to pay close attention to detail
• Good leadership skills for mentoring colleagues
• Excellent knowledge of the English, both written and spoken

Contact:
Bárbara Pinto, LinkedIn

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