Design Verification Engineer m/f/d

Texas Instruments; Freising; Vor Ort; EUR 65.000 - 85.000; Vollzeit

Zusammenfassung

A leading semiconductor company located in Freising, Germany, is looking for a highly motivated Verification Engineer to join their SR-LVB product line. The role involves executing pre-silicon verification of mixed-signal ICs, collaborating with design and test engineers, and implementing test-benches. Candidates should have a strong background in verification methodologies and analog circuits. This position offers excellent development opportunities and exposure to various engineering roles.

Qualifikationen

• Experience in mixed-signal IC verification environments.
• Familiarity with UVM-based flows.
• Understanding of analog circuits and systems.

Aufgaben

• Execute pre-silicon verification of mixed-signal ICs.
• Collaborate with design and test engineers.
• Implement test-benches and write verification plans.

Kenntnisse

Pre-silicon verification

UVM

VerilogAMS

Behavioral models

Ausbildung

Bachelor's degree in Electrical Engineering or related field

Tools

Simulation software

Verification tools

Jobbeschreibung

Why APP?

Power is everywhere! The Analog Power Products team designs and develops more than 30,000 products for the industrial, automotive, personal electronics and communications markets. Our solutions cover the entire AC/DC and DC/DC power spectrum and are leading the industry in power density, power consumption, EMI performance, and other performance metrics. Made up of six dynamic business units, APP is at the forefront of industrial and next-generation automotive trends. You will be joining the SR-LVB product line which is located in Freising, Germany and is working in the fields of inductive DCDC converters. We focus on fully integrated buck converters and controllers in the low voltage area (<7V), supporting a broad range of applications requiring ultra-low load currents as well as up to even 100A ranging from low-cost devices (<1ct) up to automotive functional safety device with digital cores with 70k gates. Join us for the opportunity to create innovative and compelling products for customers that then help create a better world.

About the Job

The SR-LVB product line is seeking for a highly motivated Verification Engineer. As a member of the Verification team, you will be part of ensuring that the devices work according to specification as well as in-system. Verification engineers work together with analog designers, digital designers, system engineers and test engineers. They are involved in the complete project cycle: scheduling tasks in the project planning phase, verifying the implementation in the design phase and supporting the validation, test and qualification team when the silicon is back. In this position you will gain or further enhance your in-depth knowledge of the latest verification methodologies and tools as well as your understanding of analog circuits.

As part of your job, you will also get exposure to other roles such as: Digital Design & Analog Design through formal learning, projects and on-the-job development experiences that will help you broaden your knowledge and accelerate your growth and success at TI.

Example products we have built are TPS62870, TPS62A01, TPS62810, TPS62880

As a Verification Engineer, the key responsibilities are the following but not limited to:

• Execute the pre-silicon verification of mixed-signal ICs in an UVM based environment (AMS/DMS)
• Collaborate closely with digital/analog designers, applications and system engineers, and manufacturing test to support pre-silicon verification efforts
• Implement test-benches to apply stimuli and checks to verify DUT behavior
• Write detailed verification plans to cover project requirements for top-level functionality, and construct test cases exercising the plan
• Evaluate system-level use-cases and re-create these in simulation
• Develop and maintain behavioral models (VerilogAMS / WREAL)
• Review the digital and analog design to provide guidance on Design for Verification architecture and features during chip development
• Simulate RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits, as well as closed-loop simulation with analog behavioral models
• Actively participate in the development and improvement of the existing verification flow