Sr. Staff/Principle ASIC Design Architect – Display Peripherals

Qualcomm; Markham; On-site; CAD 120,000 - 160,000; Full time

Job summary

A leading technology innovator is seeking a Sr. Staff/Principal Design Architect to lead architecture standards and peripheral design across mobile, XR, and automotive sectors. The ideal candidate will possess extensive experience in ASIC design with a focus on display technologies. This role requires strong problem-solving skills, a relevant degree, and a collaborative approach in a dynamic environment.

Qualifications

• Bachelor's, Master's, or PhD in relevant field with 4-6+ years of ASIC experience.
• 8+ years experience in ASIC RTL design focused on display.
• Proven expertise in bus design and interface standards.

Responsibilities

• Own end-to-end system architecture and architecture standards.
• Evaluate design process flow from high-level to ASIC.
• Write technical documentation and ensure team alignment.

Skills

ASIC design

display technologies

communication skills

problem solving

team collaboration

Education

Bachelor's degree in Computer Science, Engineering or related field

Master’s degree in Computer Science, Engineering or related field

PhD in Computer Science, Engineering or related field

Tools

Cadence

RTL Compiler

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

A leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

Responsibilities:

As Sr. Staff/Principal Design Architect for this Display IP, you will be responsible for architecture standards and peripherals design across a broad range of mobile, XR, compute, and automotive use cases. You will:

• Own end-to-end system architecture
• Determine architecture standards
• Oversee definition, design, verification, and documentation for ASIC development.
• Define module interfaces/formats for simulation.
• Evaluate all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use.
• Analyze equipment to establish operation data, conduct experimental tests, and evaluate results.
• Provide technical expertise for next generation initiatives.
• Collaborate, review and enable design and system teams to execute on dependent specifications.
• Post-silicon commercialization support and customer engineering documentation.
• Define and patent novel architectures that drive industry leadership.
• Use tools/applications (i.e., Cadence, RTL Compiler, etc.) to execute advanced architecture and design of multiple complex blocks and make suggestions for design protocol.
• Utilize advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems.
• Own the design and verification strategies of ASICs, SoC, and IP cores.
• Maintain regular communication with key team members to ensure continued alignment between team deliverables and product execution plan.
• Write technical documentation and provide technical expertise for design or project reviews and project meetings to ensure the team's best interest is represented.
• Act as a tech lead on small to large projects and own team deliverables of the project.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master’s degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Requirements:

• 8+ years of experience in ASIC RTL design with a concentration in display (CDC, FIFOs implementation, Bus implementation/verification techniques, Memory selection and control, High speed and low power design optimization, Bus interface protocols, etc).
• Extensive knowledge of display technologies used in peripherals such as DisplayPort, HDMI and/or MIPI DSI.
• Expertise in USB, PCIE and/or Thunderbolt would also be of interest.

Preferred Qualifications:

• Master’s or PhD degree in Computer Engineering or Computer Science with a significant research component and foundation in VLSI concepts.
• 15+ years ASIC design, verification, or related work experience.
• 10+ years experience with computer architecture and design tools.
• 10+ years experience with bus design and/or cache, memory controllers, low power design.
• Knowledge of peripheral interface standards such as VESA DisplayPort, DSC, MIPI, HDCP, USB, PCIE, FPDLink, GMSL, GVIF, APIX, ML, MLE, IEEE 820.3dm, IEEE1722, CTA.
• Multimedia architectures for display.
• Experience with embedded software development, including Agile Embedded software methodologies and processes.
• Experience managing SW development teams (directly or matrixed).
• Comfortable making technical and business presentations to a wide range of audiences, including to senior management.
• Ability to independently drive activities/project with internal and external cross-functional teams.
• Effective written/verbal communication and presentation skills.
• Highly motivated team player who possesses outstanding analytical skills.
• Global market experience.

Applicants:

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

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